SC2200 datasheet(343/433 Pages) NSC

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Video Processor Module (Continued)

Offset 20h-23h

Palette (Gamma Correction RAM) Data Register (R/W)

Reset Value: xxxxxxxxh

Provides the video palette data. The data can be read or written to the Gamma Correction RAM (palette) via this register. Prior to

accessing this register, an appropriate address should be loaded to the Palette Address register (F4BAR0+Memory Offset 1Ch[7:0]).

Subsequent accesses to the Palette Data register cause the internal address counter to be incremented for the next cycle.

31:8

PAL_DATA (Palette Data). Contains the read or write data for a Gamma Correction RAM (palette).

Note: When a read or write to the Gamma Correction RAM occurs, the previous output value is held for one additional DOT-

CLK period. This effect should go unnoticed during normal operation.

7:0

Reserved.

Offset 24h-27h

Reserved

Offset 28h-2Bh

Miscellaneous Register (R/W)

Reset Value: 00001400h

Configuration and control register for miscellaneous characteristics of the Video Processor.

31:13

Reserved.

PLL2_PWR_EN (PLL2 Power-Down Enable).

0: Power-down.

1: Normal.

A_PWR_DN (Analog Power-Down). Enables power-down of the PLL2 and the bandgap circuit that generates VREF.

0: Normal.

1: Power-down.

Note:

If A_PWR_DN is set to 1 without also setting DAC_PWR_DN (bit 10) to 1, an unexpected increase in power con-

sumption may result.

DAC_PWR_DN (DAC Power-Down). Powers down the internal CRT DAC.

0: Normal.

1: Power-down.

9:1

Reserved.

GAMMA_EN (Gamma Correction RAM Enable). Allows video or graphics (selected by F0BAR0+Memory Offset 04h[21])

to go to the Gamma Correction RAM.

0: Enable.

1: Disable.

Offset 2Ch-2Fh

PLL2 Clock Select Register (R/W)

Reset Value: 00000000h

Determines the characteristics of the integrated PLL2.

31:23

Reserved. Must be set to 0.

22:21

CLK_DIV_SEL (Clock Divider Select).

00: No division

01: Divide by 2

10: Divide by 4

11: Divide by 8

Divides the clock generated by the PLL2, using the programmed m (bits [14:8]) and n (bits [3:0]) values.

SEL_REG_CAL. Selects specific or previously-calculated values.

0: Values previously calculated from the CLK_SEL bits (bits [19:16]).

1: Values according to the m (bits [14:8]), n (bits [3:0]), and CLK_DIV_SEL (bits [22:21]) fields.

19:16

CLK_SEL (Clock Select). Selects frequency (in MHz) of the display clock.

0000: 25.175

0100: 50

1000: 65

1100: 108

0001: 31.5

0101: 49.5

1001: 75

1101: 135

0010: 36

0110: 56.25

1010: 78.5

1110: 27

0011: 40

0111: 44.9

1011: 94.5

1111: 24.923052

LFTC (Loop Filter Time Constant). This bit should be set when m (bits [14:8]) value is higher than 30.

Table 6-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)

Bit

Description

SC2200 Datasheet(PDF) 343 Page - National Semiconductor (TI)

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