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Video Processor Module (Continued)

VID_LIN_INV (Video Line Invert). When this bit is set, it allows the video window to be positioned at odd offsets with

respect to the first line. The values below are recommended if VID_Y_START (F4BAR0+Memory Offset 0Ch[10:0]) is an

odd (set to 1) or even (set to 0) number of lines from the start of the active display.

0: Even.

1: Odd.

Reserved: Set to 0.

CSC_FOR_VIDEO (Color Space Converter for Video). Determines whether or not the video stream from the video mod-

ule is passed through the CSC.

0: Disable. The video stream is sent "as is" to the video Mixer/Blender.

1: Enable. The video stream is passed through the CSC (for YUV to RGB conversion).

Note:

Mixing and blending configurations are created using bits [13, 11:9] of this register. See Table 6-1 "Valid Mix-

ing/Blending Configurations" on page 327.

VIDEO_BLEND_MODE (Video Blending Mode). Allows selection of the type of video (i.e., interlaced or progressive) used

for blending.

0: Progressive video used for blending.

1: Interlaced video used for blending.

Note:

Mixing and blending configurations are created using bits [13, 11:9] of this register. See Table 6-1 "Valid Mix-

ing/Blending Configurations" on page 327.

GFX_INS_VIDEO (Graphics Inside Video). This bit works in conjunction with bit COLOR_CHROMA_SEL (F4BAR0+Mem-

ory Offset 4Ch[20]). COLOR_CHROMA_SEL selects whether the graphics is used for color keying or the video data stream

is used for chroma keying. If COLOR_CHROMA_SEL = 0, graphics data is compared to the color key. If

COLOR_CHROMA_SEL = 1, video data is compared to the chroma key.

0: Outside the alpha windows, graphics or video is displayed depending on the result of the color key comparison.

1: Outside the alpha windows, only video is displayed (if COLOR_CHROMA_SEL = 0) or only graphics is displayed (if

COLOR_CHROMA_SEL = 1) color key comparison is not performed outside the alpha windows.

VID_WIN_PUSH_EN (Video Window Push Enable). Video window repositioning at an offset of 1 line below the pro-

grammed value. Facilitates line rate matching in both fields.

0: Disable. (Default)

1: Enable.

TOP_LINE_IN_ODD (Top Line in Odd Field). Allows selection of what field the top line is in.

0: Top lineisinevenfield. (Default)

1: Top line is in odd field.

Reserved.

INSERT_EN (Insert Enable). When this bit is set, the odd frame is shifted with respect to the even frame.

0: No shifting occurs.

1: The odd frame is shifted according to the offset specified in bits [2:0].

Reserved.

2:0

OFFSET (Vertical Scaler Offset). For an interlaced video stream, program a value of 100 (i.e., shift one line).

Offset 50h-53h

Cursor Color Key Register (R/W)

Reset Value: 00000000h

31:29

Reserved.

28:24

COLOR_REG_OFFSET (Cursor Color Register Offset). This field indicates a bit in the incoming graphics stream. It is

used to indicate which of the two possible cursor color registers should be used for color key matches for the bits in the

graphics stream.

23:0

CUR_COLOR_KEY (Cursor Color Key). Specifies the 24-bit RGB value of the cursor color key. The incoming graphics

stream is compared with this value. If a match is detected, the pixel is replaced by a 24-bit value from one of the Cursor

Color registers.

Offset 54h-57h

Cursor Color Mask Register (R/W)

Reset Value: 00000000h

31:24

Reserved

23:0

CUR_COLOR_MASK (Cursor Color Mask). This mask is a 24-bit value. Zeroes in the mask cause the corresponding bits

in the incoming graphics stream to be ignored.

Table 6-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)

Bit

Description

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