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SC2200 Datasheet(PDF) 347 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # SC2200
Description  Thin Client On a Chip
PDF  433 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SC2200 Datasheet(HTML) 347 Page - National Semiconductor (TI)

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Video Processor Module (Continued)
Offset 58h-5Bh
Cursor Color Register 1 (R/W)
Reset Value: 00000000h
31:24
Reserved
23:0
CUR_COLOR_REG1 (Cursor Color Register 1). Specifies a 24-bit cursor color value. This is an RGB value (for RGB
blending) or a YUV value (for YUV blending). In interlaced YUV blending mode, Y/2 value should be used.
This is one of two possible cursor color values. The COLOR_REG_OFFSET bits (F4BAR0+Memory Offset 50h[28:24])
determine a bit of the graphics data that if even, selects this color to be used.
Offset 5Ch-5Fh
Cursor Color Register 2 (R/W)
Reset Value: 00000000h
31:24
Reserved
23:0
CUR_COLOR_REG2 (Cursor Color Register 2). Specifies a 24-bit cursor color value. This is an RGB value (for RGB
blending) or a YUV value (for YUV blending). In interlaced YUV blending mode, Y/2 value should be used.
This is one of two possible cursor color values. The COLOR_REG_OFFSET bits (F4BAR0+Memory Offset 50h[28:24])
determine a bit of the graphics data that if even, selects this color to be used.
Offset 60h-63h
Alpha Window 1 X Position Register (R/W)
Reset Value: 00000000h
Note:
H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some-
times referred to as “horizontal back porch”. For more information, see the
GX1 Processor Series Datasheet.
Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
31:27
Reserved.
26:16
ALPHA1_X_END (Alpha Window 1 Horizontal End). Determines the horizontal end position of Alpha Window 1 (not inclu-
sive). This value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 1.
15:11
Reserved.
10:0
ALPHA1_X_START (Alpha Window 1 Horizontal Start). Determines the horizontal start position of Alpha Window 1. This
value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 2.
Offset 64h-67h
Alpha Window 1 Y Position Register (R/W)
Reset Value: 00000000h
Note:
V_TOTAL and V_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8340h[26:16] and 8348h[26:16], respectively). The value of (V_TOTAL – V_SYNC_END) is some-
times referred to as “vertical back porch”. For more information, see the
GX1 Processor Series Datasheet.
Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
31:27
Reserved.
26:16
ALPHA1_Y_END (Alpha Window 1 Vertical End). Determines the vertical end position of Alpha Window 1 (not inclusive).
This value is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 2.
15:11
Reserved.
10:0
ALPHA1_Y_START (Alpha Window 1 Vertical Start). Determines the vertical start position of Alpha Window 1. This value
is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1.
Offset 68h-6Bh
Alpha Window 1 Color Register (R/W)
Reset Value: 00000000h
31:25
Reserved.
24
ALPHA1_COLOR_REG_EN (Alpha Window 1 Color Register Enable). Enable bit for the color key matching in Alpha
Window 1.
1: Enable. If this bit is enabled and the alpha window is enabled, then where there is a color key match. The color value (in
bits [23:0], ALPHA1_COLOR_REG) is displayed.
0: Disable. Where there is a color key match, no blending is performed.
23:0
ALPHA1_COLOR_REG (Alpha Window 1 Color Register). Specifies the color to be displayed inside Alpha Window 1
when there is a color key match in the alpha window. This is an RGB value (for RGB blending) or a YUV value (for YUV
blending). In interlaced YUV blending mode, Y/2 value should be used.
This color is only displayed if the alpha window is enabled and bit 24 (ALPHA1_COLOR_REG_EN) is enabled.
Table 6-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description



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