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SC2200 Datasheet(PDF) 360 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # SC2200
Description  Thin Client On a Chip
PDF  433 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SC2200 Datasheet(HTML) 360 Page - National Semiconductor (TI)

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360
Revision 3.0
Electrical Specifications (Continued)
8.1.4.3
Definition of System Conditions for Measur-
ingOnParameters
The SC2200’s current is highly dependent on two func-
tional characteristics, DCLK (DOT clock) and SDRAM fre-
quency. Table 8-4 shows how these factors are controlled
when measuring the typical average and absolute maxi-
mum processor current parameters.
8.1.4.4
DC Current Measurements
Table 8-5 and Table 8-6 show the DC current measure-
ments of the SC2200. The SC2200 supports CRT and TFT
displays, but it is expected that generally only one display
interface will be used. Power consumed by the SC2200 is
different with different displays. The CRT DAC requires cur-
rent, while the TFT interface even though it has no DAC to
power, also draws current while it is active. The CRT DAC
and the TFT interface are presented as separate line items.
The chosen display type I/O current should be added to the
Typical, Absolute Maximum, and Active Idle I/O currents to
get total current.
Table 8-4. System Conditions Used to Measure SC2200’s Current Used During the "On" State
CPU Current Measurement
System Conditions
VCORE
1
VIO
1
DCLK Freq.
SDRAM Freq.
Typical Average
Nominal
Nominal
50 MHz2
Nominal
Absolute Maximum
Max
Max
135 MHz3
Max
1.
See Table 8-2 on page 358 for nominal and maximum voltages.
2.
A DCLK frequency of 50 MHz is derived by setting the display mode to 800x600x8 bpp at 75 Hz, using a display image
of vertical stripes (4-pixel wide) alternating between black and white with power management disabled.
3.
A DCLK frequency of 135 MHz is derived by setting the display mode to 1280x1024x8 bpp at 75 Hz, using a display
image of vertical stripes (1-pixel wide) alternating between black and white with power management disabled.
Table 8-5. DC Characteristics On Mode
Symbol
Parameter1
Typ Avg
Abs Max
Unit
Comments
ICC3ON
fCLK = 233 MHz, I/O Current @ VIO =3.3V
(Nominal); CPU mode = On, excludes TFT
interface contribution and CRT DAC
230
250
mA
ICC for VIO
fCLK = 266 MHz, I/O Current @ VIO =3.3V
(Nominal); CPU mode = On, excludes TFT
interface contribution and CRT DAC
240
260
fCLK = 300 MHz, I/O Current @ VIO =3.3V
(Nominal); CPU mode = On, excludes TFT
interface contribution and CRT DAC
250
270
ICOREON
fCLK = 233 MHz, Core Current @ VCORE =
1.8V (Nominal); CPU mode = On
820
990
mA
ICC for VCORE
fCLK = 266 MHz, Core Current @ VCORE =
1.8V (Nominal); CPU mode = On
900
1090
fCLK = 300 MHz, Core Current @ VCORE =
2.0V (Nominal); CPU mode = On
1050
1330
ISBON
SB Current @ VSB =3.3V(Nominal);CPU
mode = On
12
mA
ISBLON
SBL Current @ VSBL =1.8V(Nominal);CPU
mode = On
10
20
mA
SBL Current @ VSBL =2.0V(Nominal);CPU
mode = On
10
20



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