VT6305 datasheet(21/35 Pages) ETC

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Revision 0.2 March 10, 2000

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Memory Offset 1C – 1394 Bus ID...................................RO

This register maps to the 1st 32-bit word of the bus info

block.

31-0 Bus ID ...... always reads 31333934h (ASCII “1394”)

Memory Offset 20 – 1394 Bus Options.......................... RW

This register maps to the 2nd quadword of the bus info block.

Isochronous Resource Manager Capable

Not capable

Capable................................................ default

Cycle Master Capable

Not capable

Capable................................................ default

Isochronous Capable

Not capable

Capable................................................ default

Bus Manager Capable

Not capable

Capable................................................ default

Power Management Capable

Not capable ......................................... default

Capable

26-24 Reserved

...................................... always reads 0

23-16 Cycle Clock Acc

1394 Bus Management Field. This field must be

written with valid data prior to setting the “HC

Control” register “link enable” bit.

15-12 Received Block Write Request Packet Max

Length

1394 Bus Management Field. This field must be

written with valid data prior to setting the “HC

Control” register “link enable” bit. Received block

write request packets with a length greater than the

value contained in this field may generate an

“ack_type_error”.

11-8 Reserved

...................................... always reads 0

7-6

Configuration ROM Changed Since Last Bus

Reset

Configuration ROM not changed ......... default

Configuration ROM changed

5-3

Reserved

...................................... always reads 0

2-0

Max Link Speed ................................. default = 010

Memory Offset 24 – Global Unique ID High.................RW

This register maps to the 3rd 32-bit word of the bus info

block.

Contents are cleared by hardware reset but are not

affected by software reset. Read/Write if Rx44[0] is cleared,

Read/Only if Rx44[0] is set.

31-8 Node Vendor ID ......................................default = 0

1394 Bus Management Field. Must be set prior to

setting the “HC Control” register “link enable” bit.

7-0

Chip ID High ..........................................default = 0

1394 Bus Management Field. Must be set prior to

setting the “HC Control” register “link enable” bit.

Memory Offset 28 – Global Unique ID Low..................RW

This register maps to the 4th 32-bit word of the bus info

block. Contents are cleared by hardware reset but are not

affected by software reset. Read/Write if Rx44[0] is cleared,

Read/Only if Rx44[0] is set.

31-0 Chip ID Low ...........................................default = 0

1394 Bus Management Field. Must be set prior to

setting the “HC Control” register “link enable” bit.

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