VT6305 datasheet(16/35 Pages) ETC

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Revision 0.2 March 10, 2000

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1394 Host Controller Configuration Registers (Function 0)

The 1394 host controller interface follows the Open HCI

(OHCI) interface specification. There are two sets of software

accessible registers: configuration registers and memory

registers.

The configuration registers are located in the

function 0 PCI configuration space. The memory registers

are located in system memory space at offsets from the

address stored in the Base Address Register.

Configuration Space Header

Offset 1-0 - Vendor ID ....................................................RO

0-7

Vendor ID ................ (1106h = VIA Technologies)

Offset 3-2 - Device ID......................................................RO

0-7

Device ID

(0130h = VT6305 1394 Controller)

Offset 5-4 - Command.................................................... RW

15-10 Reserved

...................................... always reads 0

Fast Back-to-Back Enable ....... fixed at 0 (disabled)

SERR# Enable .......................... fixed at 0 (disabled)

Wait Cycle Control................... fixed at 0 (disabled)

Parity Error Response.............. fixed at 0 (disabled)

VGA Palette Snoop................... fixed at 0 (disabled)

Postable Memory Write Enablefixed at 0 (disabled)

Special Cycle Enable ................ fixed at 0 (disabled)

Bus Master Enable

Disable................................................. default

Enable

Memory Space Enable

Disable................................................. default

Enable Access to 1394 Memory Registers

I/O Space Enable...................... fixed at 0 (disabled)

Offset 7-6 - Status ........................................................ RWC

Detected Parity Error.......................always reads 0

Signalled System Error.....................always reads 0

Received Master Abort

No Master Abort Generated..................default

Master Abort Generated by 1394 Controller.

Set by the 1394 interface logic if it generates a

master abort while acting as a master. This

bit may be cleared by software by writing a

one to this bit position.

Received Target Abort

No Target Abort Received ....................default

Target Abort Received by 1394 Controller.

Set by the 1394 interface logic if it receives a

target abort while acting as a master. This bit

may be cleared by software by writing a one to

this bit position.

Signalled Target Abort .....................always reads 0

10-9 DEVSEL# Timing

00 Fast

01 Medium.................................................. fixed

10 Slow

11 Reserved

Data Parity Error Detected ..............always reads 0

Fast Back-to-Back Capable..............always reads 1

User Definable Features ...................always reads 0

66 MHz Capable ...............................always reads 0

4-0

Reserved

......................................always reads 0

Offset 8 - Revision ID (nnh)............................................ RO

7-0

Silicon Revision Code (0 indicates first silicon)

Offset 9 - Programming Interface (10h=OHCI) ............. RO

Offset A - Sub Class Code (00h=1394 Serial Bus) .......... RO

Offset B - Base Class Code (0Ch=Serial Bus Controller) RO

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