VT6305 datasheet(10/35 Pages) ETC

10 / 35 page

Revision 0.2 March 10, 2000

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Pinouts

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Pin Descriptions

Table 1. VT6305 Pin Descriptions

PCI Bus Interface

Signal Name

Pin No.

I/O

Signal Description

AD[31:0]

1, 2, 4, 5, 7-10,

13, 15, 17-22, 36,

39, 41-44, 46, 47,

49-51, 53, 55-58

Address / Data Bus. The standard PCI address and data lines. The address is

driven with FRAME# assertion and data is driven or received in following cycles.

CBE[3:0]#

11, 24, 35, 48

Command / Byte Enable. The command is driven with FRAME# assertion. Byte

enables corresponding to supplied or requested data are driven on following clocks.

FRAME#

Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates

that one more data transfer is desired by the cycle initiator.

DEVSEL#

Device Select.

As an output, this signal is asserted to claim PCI transactions

through positive or subtractive decoding.

As an input, DEVSEL# indicates the

response to a VT6305-initiated transaction and is also sampled when decoding

whether to subtractively decode the cycle.

TRDY#

Target Ready. Asserted when the target is ready for data transfer.

IRDY#

Initiator Ready. Asserted when the initiator is ready for data transfer.

PREQ#

127

PCI Bus Request. Asserted by the bus master to indicate to the bus arbiter that it

wants to use the bus.

PGNT#

126

PCI Bus Grant. Asserted to indicate that access to the bus is granted.

IDSEL

Initialization Device Select. IDSEL is used as a chip select during configuration

read and write cycles.

INTA#

122

Interrupt A. An asynchronous signal used to request an interrupt.

INTB#

121

Interrupt B. An asynchronous signal used to request an interrupt.

PCLK

124

PCI Clock. Timing reference for all transactions on the PCI Bus.

RESET#

123

Reset.

When detected low, an internal hardware reset is performed. PCIRST#

assertion or deassertion may be asynchronous to PCLK, however, it is recommended

that deassertion be synchronous to guarantee a clean and bounce free edge.

PAR

Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

PERR#

Parity Error. Parity error is asserted when a data parity error is detected.

SERR#

System Error. SERR# is pulsed active to indicate a system error condition.

STOP#

Stop. Asserted by the target to request the master to stop the current transaction.

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