VT6305 datasheet(29/35 Pages) ETC

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Asynchronous Transmit & Receive Context Registers

Offset 180 (Set), 184 (Clr) – Async Req Xmit Context.. RW

Offset 1A0 (Set), 1A4 (Clr) – Async Rsp Xmit Context RW

Offset 1C0 (Set), 1C4 (Clr) – Async Req Rcv Context.. RW

Offset 1E0 (Set), 1E4 (Clr) – Async Rsp Rcv Context .. RW

These registers are the Context Control registers for

Asynchronous

Transmit

Requests

and

Responses

and

Asynchronous Receive Requests and Responses, respectively.

They contain bits for control of options, operational state, and

status for a DMA context. The bit layout for both registers is

given below:

31-16 Reserved

...................................... always reads 0

Run

This bit is set and cleared by software to enable

descriptor processing for a context. The chip will

clear this bit automatically on a hardware or software

reset.

Before software sets this bit, the active bit

must be clear and the Command Pointer register for

the context must contain a valid descriptor block

address and a Z value that is appropriate for the

descriptor block address.

Software may stop the chip from further processing

of a context by clearing this bit. When cleared, the

chip will stop processing of the context in a manner

that will not impact the operation of any other

context or DMA controller.

This may require a

significant amount of time. If software clears a run

bit for an isochronous context while the chip is

processing a packet for the context, it will continue

to receive or transmit the packet and update the

descriptor status. It will then stop at the conclusion

of that packet. If the run bit is cleared for a non-

isochronous context, the chip will stop processing at

a convenient point and put the descriptors in a

consistent state (e.g., status updated if a packet was

sent and acknowledged).

Clearing the bit may have other side effects that are

DMA controller dependent. This is described in the

sections that cover each of the DMA controllers.

14-13 Reserved

...................................... always reads 0

Wake

............................................ default = 0

When software adds to a list of descriptors for a

context, the chip may have already read the

descriptor that was at the end of the list before it was

updated. This bit provides a semaphore to indicate

that the list may have changed.

If the chip had fetched a descriptor and the indicated

branch address had a Z value of zero, it will reread

the pointer value when the wake bit is set. If, on the

reread, the Z value is still zero, then the end of the

list has been reached and the chip will clear the

active bit. If, however, the Z value is now non-zero,

the chip will continue processing. If the wake bit is

set while the chip is active and has a Z value of non-

zero, it takes no special action.

The chip will clear this bit before it reads or rereads

a descriptor. The wake bit should not be set while

the run bit is zero.

Dead

............................................default = 0

This bit is set by the chip to indicate a fatal error in

processing a descriptor. When set, the active bit is

cleared. This bit is cleared when software clears the

run bit or on a hardware or software reset.

Active

............................................default = 0

This bit is set by the chip when software sets the run

bit or sets the wake bit while the run bit is set. The

chip will clear this bit:

when a branch is indicated by a descriptor but

the Z value of the branch address is 0

when software clears the run bit and the chip

has reached a safe stopping point

while the dead bit is set

after a hardware or software reset

for asynchronous transmit contexts (request

and response), when a bus reset occurs

When this bit is 0 and the run bit is 0, the chip will

set the Interrupt Event bit for the context.

9-8

Reserved

......................................always reads 0

7-5

Speed (Async Receive Contexts Only)

This field indicates the speed at which the packet

was received or transmitted:

000 100 Mbits/sec

001 200 Mbits/sec

010 400 Mbits/sec

011 -reserved-

1xx -reserved-

4-0

Ack / Err Code........................................default = 0

Following an “Output Last” command, the received

“Ack Code” or “Event Error Code” is indicated in

this field.

Possible values are:

“Ack Complete”,

“Ack Pending”, Ack Busy X”, “Ack Data Error”,

“Ack Type Error”, “Event Tcode Error”, “Event

Missing Ack”, “Event Underrun”, “Event Descriptor

Read”, “Event Data Read”, “Event Timeout”, “Event

Flushed”, and “Event Unknown” (see “Table 3.

Packet Event Codes” on the following page for

descriptions and values for these codes).

Offset 18C – Async Req Xmit Context Command Ptr ..RW

Offset 1AC – Async Rsp Xmit Context Command Ptr..RW

Offset 1CC – Async Req Rcv Context Command Ptr....RW

Offset 1EC – Async Rsp Rcv Context Command Ptr ....RW

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