are applied to the READ pin in order to transfer the pixel voltages to the VIDEO_P/N pins. The first 3 Read Clock pulses, designated with

1, 2 and 3 in Figure 10, are used to pre-load the pipeline. Thus the first 3 pixel voltage values on VIDEO_P/N can be ignored. The subse-

quent Read Clock pulses, designated with P0 ... PN in Figure 10, transfer the pixel voltage values through the video amplifier to the

VIDEO_P/N pins.

first. The transmission of the last pixel is indicated by a high state of the pin ANA_TEST0 upon the last Read Clock pulse rising edge.

ANA_TEST0 goes low again upon the following rising edge at READ.

The signal DATA_RDY remains high as long as there is at least one frame stored in the CCD frame store. If no more frames are stored ex -

cept the one that is currently read out, the signal DATA_RDY goes to low state on the first positive Read Clock edge (see Figure 10). If no

frame is stored, the chip does nothing upon a Read Pulse.

IMPORTANT

–

It is important to sample the analog output signal of the vide amplifier just before the rising edge of the next read pulse. This time

point allows the readout circuits and the video amplifier to be fully settled. Also at this time point, the lowest possible readout

noise can be achieved.

–

The following time periods shall never overlap in any multi frame acquisition or by parallel reading during exposure:

5.5. Readout configuration

Read-out can be configured through the configuration pins (see section 4.1). Depending on binning and ROI selection, different numbers

of pixels are available for read-out. E.g. if binning of 2 is selected, only 512 values can be read out because always two pixels are binned.

Thus, only 512 + 3 Read Clock pulses must be applied in this example. The following table shows the number of Read Clock pulses ac -

cording to the configuration:

ROI_SEL pin

HOR_BIN pin

L

L

512+3

L

M

1024+3

L

H

256+3

H

L

256+3

H

M

512+3

H

H

128+3

Table 4: ROI_SEL/HOR_BIN settings

5.6. Periodic flushing

As explained in section 5.2., the imager is photosensitive all the time. So it constantly converts incoming light into charge. If the pixel field

(the CCD) is not flushed periodically, excessive charge can be generated which may spill over from the pixel field to neighboring circuits,

e.g. the frame store buffers. Thus, periodic flushing by applying a CLR_PIX pulse during the time no images are acquired is highly recom -

received and how long is the time between two SHUTTER pulses.

For a given application, it is a good idea to evaluate the setup first before the system software is implemented. During evaluation, one

measure of the charge generated in the pixel by applying a SHUTTER signal with the length of the time between the intended acquisition

of two images shall be executed. If the maximal pixel value exceeds 90% of full well (= 90% of output swing), it is highly recommended to

place additional CLR_PIX pulses during the time where no image acquisition takes place.

In power-down mode, the CCD is not photo-sensitive and therefore no charge is collected. However, the transition from power-down mode

to operation flushes the CDD and the frame store automatically.

5.7. Clearing the CCD pixel field and the CCD frame store with CLR_DATA

The frames stored in the CCD pixel field and the CCD frame store can be erased simultaneously by a pulse on CLR_DATA with a minim-

pixel field are cleared, the chip is ready to acquire new images.

A rising edge on CLR_DATA also aborts an on-going read-out and a new image acquisition can be initiated immediately. As long as

DATA_RDY is not asserted (upon the new image acquisition), the read-out of the frame in the CDS can be continued without any impact

on the frame (for multi-frame operation see section 5.3)

A rising edge of CLR_DATA during a shift operation might be ignored and is therefore to avoid. It is allowed to assert SHUTTER and

CLR_DATA at the same time.

Please note that the frame store buffers also collect charge even if there is no operation with the CCD. This is due to dark current which

can also flow into the frame store buffer elements. Thus, the frame store buffer should also be cleared (erased) regularly if there is no ac -

quisition and readout within 100ms.

© 2016 ESPROS Photonics Corporation

Characteristics subject to change without notice

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