91C94 datasheet(90/120 Pages) SMSC

Part #	91C94

Description	ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

PDF	120 Pages

Scroll/Zoom	100%

Manufacturer	SMSC [SMSC Corporation]

Direct Link	http://www.smsc.com

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90 / 120 page

For example, if an odd pointer value is loaded,

first a byte is pre-fetched into the FIFO, and

immediately

full

word

pre-fetched

completing three bytes into the FIFO. If the CPU

reads a word, one byte will be left again a new

word is pre-fetched.

In the case of write, if an odd pointer value is

loaded, and a full word is written, the FIFO

holds two bytes, the first of which is immediately

written into an odd memory location. If by that

time another byte or word

was written, there will be two or three bytes in

the FIFO and a full word can be written into the

now even memory address.

When a CSMA/CD cycle begins, the arbiter will

route the CSMA/CD DMA addresses to the MMU

as well as the packet number associated with

the operation in progress. In full-duplex mode,

receive and transmit requests are alternated in

such a way that the CPU arbitration cycle time

is not affected.

91C94 Datasheet(PDF) 90 Page - SMSC Corporation