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WM8235 Datasheet(PDF) 153 Page - Cirrus Logic |
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WM8235 Datasheet(HTML) 153 Page - Cirrus Logic |
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153 / 154 page  WM8235 Rev 4.6 153 REVISION HISTORY DATE REV ORIGINATOR CHANGES PAGE 16/11/10 1.0 AA/NB First Release 08/12/11 3.0 JMacD Product status updated to Pre-Production 11/12/11 3.0 AA Corrected DAC description 4-bit to 8bit Corrected temperature range to -40 Corrected PGAFS characteristics Corrected Supply currents Added test conditions for TG output Corrected Clamp timing diagram Corrected Signal flow summary (removed INVOP description) Corrected Channel ID description INP to IN Corrected TG MASK description Corrected Register Map (PGAFS) 1 5,8 9,10 11 11 24 27 30 34 41,48 01/02/12 3.1 JMacD Update to Recommended External Component Values – (C9) 0.1uF changed to 0.01uF 124 20/02/12 3.2 AA/JMacD Corrected Parameter name and Register name for RLCDAC 10,41 20/02/12 3.2 AA/JMacD Corrected RLCDAC resolution 10 14/12/12 4.0 AA Added channel to channel offset matching specifcation Corrected offset DAC INL DNL spec Corrected supply current for full power down mode Updated timing specificationCorrected figure for ADC INPUT BLACK LEVEL ADJUST Corrected figure for overall signal flow Added description for ADC, PGA Bias Current Control. Added description for PLL DLL setup Added description for 3pair LVDS format Added LVDS output order Corrected TG timing diagram Added EXTENDED REGISTERES Corrected description for R28 Corrected description for R128,R129 9 10 11 15,17,36-38 21 22 22 23 29-33 34 36,37 54,131 65 83 17/02/14 4.1 AA Corrected description of conversion rate Corrected description of reference DAC resolution Updated test condition for output noise specification Corrected device ID descriptions (Table 2 and Table 3) Corrected MCLK High/Low period Corrected RESET CLAMPING description Corrected CDS/Non-CDS PROCESSING description Updated PLL and DLL setting table Corrected TG-master/slave mode timing chart Added TGSYNC low period specification Added description for LINE BY LINE operation Added description for TEST PATTERN GENERATOR Added description for Register setting procedure 1 1 9 13,14 15 18,19 20 23 39,40 40 51,52,62,79 53,54,76 55~61 |
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