WM8255 datasheet(7/49 Pages) CIRRUS

7 / 49 page

WM8255

Production Data

PD, Rev 4.7, August 2013

ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz, mode 1 unless otherwise stated.

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)

Full-scale input voltage range

(see Note 1)

Max Gain

Min Gain

0.24

2.56

Vp-p

Input signal limits (see Note 2)

VIN

AVDD1

Full-scale transition error

Gain = 0dB;

PGA[7:0] = 07(hex)

-50

+50

Zero-scale transition error

Gain = 0dB;

PGA[7:0] = 07(hex)

-50

+50

Differential non-linearity

DNL

1.5

LSB

Integral non-linearity

INL

LSB

Input referred noise

LSB rms

References

Upper reference voltage

VRT

2.05

Lower reference voltage

VRB

1.05

Diff. reference voltage (VRT-VRB)

VRTB

1.0

Output resistance VRT, VRB, VRX



VRLC/Reset-Level Clamp (RLC)

RLC switching impedance

100



VRLC short-circuit current

VRLC output resistance



VRLC Hi-Z leakage current

VRLC = 0 to AVDD1

A

RLCDAC resolution

bits

RLCDAC step size

VRLCSTEP

0.24

V/step

RLCDAC output voltage at

code 0(hex)

VRLCBOT

0.3

RLCDAC output voltage at

code F(hex)

VRLCTOP

3.9

Offset DAC, Monotonicity Guaranteed

Resolution

bits

Differential non-linearity

DNL

0.6

LSB

Integral non-linearity

INL

LSB

Step size

1.96

mV/step

Output voltage

Code 00(hex)

Code FF(hex)

-220

+220

-250

+250

-280

+280

Notes:

Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input range.

Input signal limits are the limits within which the full-scale input voltage signal must lie.

WM8255 Datasheet(PDF) 7 Page - Cirrus Logic

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