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WM8255 Datasheet(PDF) 43 Page - Cirrus Logic |
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WM8255 Datasheet(HTML) 43 Page - Cirrus Logic |
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43 / 49 page  WM8255 Production Data w PD, Rev 4.7, August 2013 43 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION 4:3 LEDIRNGG [1:0] 00 Coarse LED current range during imaging for Green LED 5 Reserved 0 Must be set to zero 7:6 STATERST [1:0] 11 State reset. Sets the number of states to be used. 00 = State_0 only 01 = State_0 to State_1 10 = State_0 to State_2 11 = State_0 to State_3 Setup Register 9 1:0 LEDIRNGB [1:0] 00 Coarse LED current range during imaging for Blue LED 2 Reserved 0 Must be set to zero 3 REQLEDST 0 If LEDSTART is to be used this register must be set high 4 MONOTG 0 When MONOMODE=0 this register has no effect. When set high allows the TG pin to restart the colour sequence when in mono mode. 5 MONOMODE 0 When set, puts the LED control in to monochrome (composite mode) 7:6 ILIMITEN[1:0] 00 Specifies the mode of operation of current limiting of the LED DAC. See Table 4 for details. Setup Register 10 1:0 STATE0[1:0] 00 Sets the State 0 colour setting. Red = 00 Green = 01 Blue = 10 Off = 11 3:2 STATE1[1:0] 01 Sets the State 1 colour setting. Red = 00 Green = 01 Blue = 10 Off = 11 5:4 STATE2[1:0] 10 Sets the State 2 colour setting. Red = 00 Green = 01 Blue = 10 Off = 11 7:6 STATE3[1:0] 11 Sets the State 3 colour setting. Red = 00 Green = 01 Blue = 10 Off = 11 Setup Register 11 7:0 LEDPWMPER [7:0] (LSBs) 00000000 Sets the LSBs of the maximum value for the LED PWM period. [7:0] Setup Register 12 3:0 LEDPWMPER [11:8] (MSBs) 0000 Sets the MSBs of the maximum value for the LED PWM period. [11:8] 7:4 CLKDIV [3:0] 0000 Sets the division of MCLK applied to the PWM counter. Setup Register 13 7:0 LEDPWMDCR [7:0] (LSBs) 00000000 Sets the LSBs of the LED PWM Duty Cycle for the RED LED. [7:0] Setup Register 14 7:0 LEDPWMDCG [7:0] (LSBs) 00000000 Sets the LSBs of the LED PWM Duty Cycle for the GREEN LED. [7:0] Offset DAC (Red) 7:0 DACR[7:0] 10000000 Red channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Green) 7:0 DACG[7:0] 10000000 Green channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Blue) 7:0 DACB[7:0] 10000000 Blue channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (RGB) 7:0 DAC[7:0] A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value. Setup Register 15 7:0 LEDPWMDCB [7:0] (LSBs) 00000000 Sets the LSBs of the LED PWM Duty Cycle for the BLUE LED. [7:0] Setup Register 16 3:0 LEDPWMDCR [11:8] (MSBs) 0001 Sets the MSBs of the LED PWM Duty Cycle for the RED LED. [11:8] The LEDPWMDCR must not be set to zero (MSB and LSB both zero) 7:4 LEDPWMDCG [11:8] (MSBs) 0001 Sets the MSBs of the LED PWM Duty Cycle for the GREEN LED. [11:8] The LEDPWMDCG must not be set to zero (MSB and LSB both zero) Set up Register 17 3:0 LEDPWMDCB [11:8] (MSBs) 0001 Sets the MSBs of the LED PWM Duty Cycle for the BLUE LED. [11:8] The LEDPWMDCB must not be set to zero (MSB and LSB both zero) 7:4 LEDSTART [3:0] 0000 Sets the LSBs of the 7 bit LEDSTART time. [3:0] |
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