WM8255 datasheet(42/49 Pages) CIRRUS

42 / 49 page

Production Data

WM8255

PD, Rev 4.7, August 2013

BIT

BIT NAME(S)

DEFAULT

DESCRIPTION

Setup

POSNEG

When VSMPDET = 0 this bit has no effect.

When VSMPDET = 1 this bit controls whether positive or negative edges

are detected:

0 = Negative edge on VSMP pin is detected and used to generate

internal timing pulse.

1 = Positive edge on VSMP pin is detected and used to generate

internal timing pulse.

See Figure 27 for further details.

2BITOP

Changes the digital output from 4 bit muxed to 2 bit muxed output.

INVOP

Digitally inverts the polarity of output data.

0 = negative going video gives negative going output,

1 = negative-going video gives positive going output data.

VRLCEXT

When set powers down the RLCDAC, changing its output to Hi-Z,

allowing VRLC/VBIAS to be externally driven.

RLCINT

This bit is used to determine whether Reset Level Clamping is enabled.

0 = RLC disabled, 1 = RLC enabled.

Reserved

Must be set to zero.

7:6

DEL[1:0]

Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC

clock period = 3 MCLK periods.

00 = Minimum latency

01 = Delay by one ADC clock

period

10 = Delay by two ADC clock periods

11 = Delay by three ADC clock periods

Setup

3:0

RLCV[3:0]

0011

Controls RLCDAC driving VRLC pin to define single ended signal

reference voltage or Reset Level Clamp voltage. See Electrical

Characteristics section for ranges.

5:4

CDSREF[1:0]

CDS mode reset timing adjust.

00 = Advance 1 MCLK period

01 = Normal

10 = Retard 1 MCLK period

11 = Retard 2 MCLK periods

7:6

INTM[1:0]

Colour selection bits used in internal modes.

00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.

See Table 1 for details.

Software

Reset

Any write to Software Reset causes all cells (including LED) to be reset.

It is recommended that a software reset be performed after a power-up

before any other register writes.

Setup

2:0

VDEL[2:0]

000

When VSMPDET = 0 these bits have no effect.

When VSMPDET = 1 these bits set a programmable delay from the

detected edge of the signal applied to the VSMP pin. The internally

generated pulse is delayed by VDEL MCLK periods from the detected

edge.

See Figure 27, Internal VSMP Pulses Generated for details.

5:3

Reserved

000

Must be set to zero

LEDIMAX

Sets the maximum current limit to one of two ranges (see electrical

characteristics section).

Reserved

Must be set to zero

Setup

7:0

LEDIDACR [7:0]

00100000

Fine LED current during imaging for Red LED

Setup

7:0

LEDIDACG [7:0]

00100000

Fine LED current during imaging for Green LED

Setup

7:0

LEDIDACB [7:0]

00100000

Fine LED current during imaging for Blue LED

Setup

1:0

LEDIRNGR [1:0]

Coarse LED current range during imaging for Red LED

Reserved

Must be set to zero

WM8255 Datasheet(PDF) 42 Page - Cirrus Logic

WM8255 Datasheet(HTML) 42 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL