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WM8255 Datasheet(PDF) 12 Page - Cirrus Logic |
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WM8255 Datasheet(HTML) 12 Page - Cirrus Logic |
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12 / 49 page ![]() Production Data WM8255 w PD, Rev 4.7, August 2013 12 PWM TIMING Figure 4 PWM Timing Test Conditions AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PWM LED Current Drive Control PWM Period tPWMPER (CLKDIV+1) * LEDPWMPER * tPER ns PWM Duty Cycle LEDPWMDC/ LEDPWMPER - PWM Period Resolution (CLKDIV +1) * tPER ns PWM Period Range (CLKDIV +1) * 4096 * tPER ns PWM Duty Cycle Resolution (CLKDIV +1) * tPER ns PWM Duty Cycle Range (CLKDIV +1) * 4096 * tPER ns PWM Enable Coarse Adjust tPWMMaxCount tPWMPER*1 tPWMPER *128 ns LEDSTART set-up time TLEDSU 6 ns LEDSTART hold time TLEDH 3 ns TG set-up time tTGSU 6 ns TG hold time tTGH 3 ns PWM Rise / Fall Time tPWMR /tPWMF 1 5 us Minimum blank period tBLANK 25 us Notes: 1. For LED Current Drive Description refer to Page 17. 2. The Blank period starts on the 2 nd falling edge of MCLK after TG goes high. 3. CLKDIV, LEDPWMPER and LEDPWMDC are register settings. For further details see Table 10. |
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