WM8255 datasheet(25/49 Pages) CIRRUS

25 / 49 page

WM8255

Production Data

PD, Rev 4.7, August 2013

Figure 17 Current Steering Switching

LED CURRENT DRIVE CURRENT PWM CONTROL

During each sequence state, the LED control module can be pulsed by Pulse Width Modulating

(PWM) the LED current drive. For each sequence state, the PWM frequency, duty cycle, and number

of PWM cycles can be configured.

The PWM controller consists of two blocks; the MCLK divider and the PWM counter. The MCLK

divider divides the MCLK by an amount set by the register CLKDIV.

The divided MCLK is then used to clock the PWM counter. The PWM counter will increment until it

reaches its maximum count set by the register LEDPWMPER. At this point, the PWM counter will

reset to zero, then continue to increment. This will set the period of the PWM control.

As the PWM counter is incremented, its state is compared with the duty cycle setting, which is set by

the value in register LEDPWMDC. PWMCtrl is set while the counter value is smaller than the duty

cycle setting. When the counter is larger than or equal to the duty cycle, PWMCTRL is reset for the

rest of the PWM period. This will set the duty cycle of the PWM control.

The reset of the PWM counter will increment the LEDEnable counter. When the LEDEnable counter

has reached LEDENSTART, PWMEn is set high, which allows PWMCtrl to control the LED current

drive. The LEDEnable counter will continue to increment until it has reached LEDENSTOP. At this

point PWMEn is set low, which stops PWMCtrl from controlling the LED current drive. This will set the

number of cycles of the PWM control.

The PWM frequency is defined by LEDPWMPER and the divider CLKDIV. LEDPWMPER and

CLKDIV may be calculated as the nearest integral of the MCLK frequency divided by the PWM

frequency. If the maximum value of LEDPWMPER would reach its maximum before the desired

PWM period is achieved, CLKDIV should be incremented to scale LEDPWMPER correctly.

The PWM duty cycle is defined by LEDPWMDC and CLKDIV. For a chosen PWM frequency, an

integral number of PWM cycles for the period of TG may be calculated. The range of the PWM period

and the duty cycle can be up to (2^4 X 2^12) MCLK cycles.

WM8255 Datasheet(PDF) 25 Page - Cirrus Logic