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AD4003/AD4007/AD4011

Data Sheet

Rev. B | Page 22 of 38

DRIVER AMPLIFIER CHOICE

Although the AD4003/AD4007/AD4011 are easy to drive, the

driver amplifier must meet the following requirements:



The noise generated by the driver amplifier must be kept

low enough to preserve the SNR and transition noise perfor-

mance of the AD4003/AD4007/AD4011. The noise from

the driver is filtered by the single-pole, low-pass filter of

the AD4003/AD4007/AD4011 analog input circuit made

by RIN and CIN or by the external filter, if one is used. Because

the typical noise of the AD4003/AD4007/AD4011 is

31.5 μV rms, the SNR degradation due to the amplifier is

























)

(

(31.5

31.5

log

LOSS

SNR

where:

f−3 dB is the input bandwidth, in megahertz, of the

AD4003/AD4007/AD4011 (10 MHz) or the cutoff

frequency of the input filter, if one is used.

N is the noise gain of the amplifier (for example, 1 in buffer

configuration).

eN is the equivalent input noise voltage of the op amp in

nV/√Hz.



For ac applications, the driver must have a THD performance

commensurate with the AD4003/AD4007/AD4011.



For multichannel multiplexed applications, the driver

amplifier and the analog input circuit of the AD4003/

AD4007/AD4011 must settle for a full-scale step onto the

capacitor array at an 18-bit level (0.000384%, 3.84 ppm). In

the data sheet of the amplifier, settling at 0.1% to 0.01% is

more commonly specified. This setting may differ

significantly from the settling time at an 18-bit level and

must be verified prior to driver selection.

Single to Differential Driver

For applications using a single-ended analog signal, either

bipolar or unipolar, the ADA4940-1 single-ended to differential

driver allows a differential input to the device. The schematic is

shown in Figure 36.

High Frequency Input Signals

The AD4003/AD4007/AD4011 ac performance over a wide

input frequency range using a 5 V reference voltage is shown in

Figure 39 and Figure 40. Unlike other traditional SAR ADCs,

the AD4003/AD4007/AD4011 maintain exceptional ac perfor-

mance for input frequencies up to the Nyquist frequency with

minimal performance degradation. Note that the input frequency

is limited to the Nyquist frequency of the sample rate in use.

102

100

17.0

15.5

16.5

14.5

15.0

16.0

14.0

100k

10k

INPUT FREQUENCY (Hz)

ENOB

SINAD

SNR

Figure 39. SNR, SINAD, and ENOB vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V,

VREF = 5 V, 25°C

–90

–105

–95

–115

–110

–100

–120

120

105

115

100

110

100k

10k

INPUT FREQUENCY (Hz)

THD

SFDR

Figure 40. THD and SFDR vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V,

VREF = 5 V, 25°C

Multiplexed Applications

The AD4003/AD4007/AD4011 significantly reduce system

complexity and cost for multiplexed applications that require

superior performance in terms of noise, power, and throughput.

Figure 41 shows a simplified block diagram of a multiplexed

data acquisition system including a multiplexer, an ADC driver,

and the precision SAR ADC.

SAR ADC

ADC

DRIVER

MULTIPLEXER

Figure 41. Multiplexed Data Acquisition Signal Chain Using the

AD4003/AD4007/AD4011

Switching multiplexer channels typically results in large voltage

steps at the ADC inputs. To ensure an accurate conversion result,

the step must be given adequate time to settle before the ADC

samples its inputs (on the rising edge of CNV). The settling

time is dependent on the drive circuitry (multiplexer and ADC

driver), RC filter values, and the time when the multiplexer

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