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AD4003/AD4007/AD4011

Data Sheet

Rev. B | Page 34 of 38

CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is typically used when a single AD4003/AD4007/

AD4011 device is connected to an SPI-compatible digital host

with an interrupt input (IRQ), and when it is desired to keep

CNV, which samples the analog input, independent of the signal

used to select the data reading. This independence is particularly

important in applications where low jitter on CNV is desired.

The connection diagram is shown in Figure 63, and the

corresponding timing diagram is shown in Figure 64.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback. If SDI and CNV are low, SDO is

driven low. Prior to the minimum conversion time, SDI can

select other SPI devices, such as analog multiplexers; however,

SDI must be returned low before the minimum conversion time

elapses and then held low for the maximum possible conversion

time to guarantee the generation of the busy signal indicator.

When the conversion is complete, SDO goes from high impedance

to low impedance. With a pull-up resistor of 1 kΩ on the SDO

line, this transition can be used as an interrupt signal to initiate

the data readback controlled by the digital host. The AD4003/

AD4007/AD4011 then enter the acquisition phase and power

down. The data bits are then clocked out, MSB first, by subsequent

SCK falling edges. The data is valid on both SCK edges.

Although the rising edge can capture the data, a digital host

using the SCK falling edge allows a faster reading rate, provided

it has an acceptable hold time. After the optional 19th SCK

falling edge or when SDI goes high (whichever occurs first),

SDO returns to high impedance.

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

IRQ

VIO

1kΩ

CS1

AD4003/AD4007/

AD4011

Figure

63. CS Mode, 4-Wire with Busy Indicator Connection Diagram

SDO

D17

D16

tDIS

SCK

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

tEN

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

SDI

CNV

tSSDICNV

tHSDICNV

tQUIET2

Figure 64. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram

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