AD4011 datasheet(24/38 Pages) AD

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AD4003/AD4007/AD4011

Data Sheet

Rev. B | Page 24 of 38

–85

–90

–100

–110

–95

–105

–115

–120

–125

INPUT FREQUENCY (KHz)

1kΩ HIGH-Z DISABLED

1kΩ HIGH-Z ENABLED

510Ω HIGH-Z DISABLED

510Ω HIGH-Z ENABLED

150Ω HIGH-Z DISABLED

150Ω HIGH-Z ENABLED

Figure 44. THD vs. Input Frequency for Various Source Impedance, VDD = 1.8

V, VIO = 3.3 V, VREF = 5 V, 25°C

Figure 45 and Figure 46 show the AD4003/AD4007/AD4011

SNR and THD performance using the ADA4077-1 (supply

current per amplifier (ISY) = 400 μA) and ADA4610-1

(ISY = 1.5 mA per amplifier) precision amplifiers when driving the

AD4003/AD4007/AD4011 at full throughput for high-Z mode

enabled and disabled with various RC filter values. These amplifiers

achieve 96 dB to 99 dB typical SNR and better than −110 dB

THD with high-Z enabled. THD is approximately 10 dB better

with high-Z mode enabled, even for large R values. SNR maintains

close to 99 dB even with a very low RC filter bandwidth cutoff.

When high-Z mode is enabled, the ADC consumes approximately

2 mW per MSPS extra power; however, this is still significantly

lower than using dedicated ADC drivers like the ADA4807-1.

For any system, the front end usually limits the overall ac/dc

performance of the signal chain. It is evident from the data sheets

of the selected precision amplifiers, shown in Figure 45 and

Figure 46, that their own noise and distortion performance

dominates the SNR and THD specification at a certain input

frequency.

100

260kHz

1.3kΩ

470pF

498kHz

680Ω

470pF

2.27MHz

390Ω

180pF

1.3MHz

680Ω

180pF

4.42MHz

200Ω

180pF

RC FILTER BANDWIDTH (Hz)

RESISTOR (Ω), CAPACITOR (pF)

ADA4077-1 HIGH-Z DISABLED

ADA4077-1 HIGH-Z ENABLED

ADA4610-1 HIGH-Z DISABLED

ADA4610-1 HIGH-Z ENABLED

Figure 45. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers,

fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V, VIO =

3.3 V, VREF = 5 V, 25°C

–80

–84

–92

–100

–88

–96

–104

–112

–108

–116

–120

260kHz

1.3kΩ

470pF

498kHz

680Ω

470pF

2.27MHz

390Ω

180pF

1.3MHz

680Ω

180pF

4.42MHz

200Ω

180pF

RC FILTER BANDWIDTH (Hz)

RESISTOR (Ω), CAPACITOR (pF)

ADA4077-1 HIGH-Z DISABLED

ADA4077-1 HIGH-Z ENABLED

ADA4610-1 HIGH-Z DISABLED

ADA4610-1 HIGH-Z ENABLED

Figure 46. THD vs. RC Filter Bandwidths for Various Precision ADC Drivers,

fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled) VDD = 1.8 V, VIO =

3.3 V, VREF = 5 V, 25°C

Long Acquisition Phase

The AD4003/AD4007/AD4011 also feature a very fast

conversion time of 290 ns, which results in a long acquisition

phase. The acquisition is further extended by a key feature of the

AD4003/AD4007/AD4011; the ADC returns back to the

acquisition phase typically 100 ns before the end of the conversion.

This feature provides an even longer time for the ADC to acquire

the new input voltage. A longer acquisition phase reduces the

settling requirement on the driving amplifier, and a lower

power/bandwidth amplifier can be chosen. The longer acquisition

phase means that a lower RC filter (represented by R and C in

Figure 33 and Figure 36) cutoff can be used, which means a

noisier amplifier can also be tolerated. A larger value of R can

be used in the RC filter with a corresponding smaller value of C,

reducing amplifier stability concerns without affecting distortion

performance significantly. A larger value of R also results in

reduced dynamic power dissipation in the amplifier.

See Table 10 for details on setting the RC filter bandwidth and

choosing a suitable amplifier.

VOLTAGE REFERENCE INPUT

A 10 μF (X7R, 0805 size) ceramic chip capacitor is appropriate

for the optimum performance of the reference input.

For higher performance and lower drift, use a reference such as

the ADR4550. Use a low power reference such as the ADR3450

at the expense of a slight decrease in the noise performance. It is

recommended to use a reference buffer, such as the ADA4807-1,

between the reference and the ADC reference input. It is important

to consider the optimum capacitance necessary to keep the

reference buffer stable as well as to meet the minimum ADC

requirement stated previously in this section (that is, a 10 μF

ceramic chip capacitor, CREF).

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