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Data Sheet

AD4003/AD4007/AD4011

Rev. B | Page 25 of 38

POWER SUPPLY

The AD4003/AD4007/AD4011 use two power supply pins: a core

supply (VDD) and a digital input/output interface supply (VIO).

VIO allows direct interface with any logic between 1.8 V and

5.5 V. To reduce the number of supplies needed, VIO and VDD

can be tied together for 1.8 V operation. The ADP7118 low noise,

CMOS, low dropout (LDO) linear regulator is recommended to

power the VDD and VIO pins. The AD4003/AD4007/AD4011

are independent of power supply sequencing between VIO and

VDD. Additionally, the AD4003/AD4007/AD4011 are insensitive

to power supply variations over a wide frequency range, as

shown in Figure 47.

100

10k

100k

FREQUENCY (Hz)

Figure 47. PSRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C

The AD4003/AD4007/AD4011 power down automatically at

the end of each conversion phase; therefore, the power scales

linearly with the sampling rate. This feature makes the device

ideal for low sampling rates (even a few samples per second)

and battery-powered applications. Figure 48 shows the

AD4003/AD4007/AD4011 total power dissipation and

individual power dissipation for each rail.

100k

100

10k

0.1

0.01

1M 2M

100k

10k

100

THROUGHPUT (SPS)

VDD

VIO

REF

TOTAL POWER

POWER DISSIPATION MEASUREMENTS

APPLY TO EACH PRODUCT OVER ITS

SPECIFIED THROUGHPUT RANGE.

Figure 48. Power Dissipation vs. Throughput, VDD = 1.8 V, VIO = 3.3 V,

VREF = 5 V, 25°C

DIGITAL INTERFACE

Although the AD4003/AD4007/AD4011 have a reduced

number of pins, they offer flexibility in their serial interface

modes. The AD4003/AD4007/AD4011 can also be programmed

via 16-bit SPI writes to the configuration registers.

When in CS mode, the AD4003/AD4007/AD4011 are compatible

with SPI, QSPI™, MICROWIRE®, digital hosts, and DSPs. In this

mode, the AD4003/AD4007/AD4011 can use either a 3-wire or

4-wire interface. A 3-wire interface using the CNV, SCK, and

SDO signals minimizes wiring connections, which is useful, for

instance, in isolated applications. A 4-wire interface using the

SDI, CNV, SCK, and SDO signals allows CNV, which initiates the

conversions, to be independent of the readback timing (SDI).

This interface is useful in low jitter sampling or simultaneous

sampling applications.

The AD4003/AD4007/AD4011 provide a daisy-chain feature

using the SDI input for cascading multiple ADCs on a single

data line, similar to a shift register.

The mode in which the device operates depends on the SDI

level when the CNV rising edge occurs. CS mode is selected if

SDI is high, and daisy-chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, daisy-chain mode is always selected.

In either 3-wire or 4-wire mode, the AD4003/AD4007/AD4011

offer the option of forcing a start bit in front of the data bits. This

start bit can be used as a busy signal indicator to interrupt the

digital host and trigger the data reading. Otherwise, without a

busy indicator, the user must time out the maximum conversion

time prior to readback.

The busy indicator feature is enabled in CS mode if CNV or SDI

is low when the ADC conversion ends.

The state of the SDO on power-up is either low or high-Z

depending on the states of CNV and SDI, as shown in Table 11.

Table 11. State of SDO on Power-Up

CNV

SDI

SDO

Low

High-Z

The AD4003/AD4007/AD4011 have turbo mode capability in

both 3-wire and 4-wire mode. Turbo mode is enabled by writing

to the configuration register and replaces the busy indicator feature

when enabled. Turbo mode allows a slower SPI clock rate, making

interfacing simpler. The maximum throughput of 2 MSPS for

the AD4003 can be achieved only with turbo mode enabled and

a minimum SCK rate of 75 MHz. The SCK rate must be

sufficiently fast to ensure the conversion result is clocked out

before another conversion is initiated. The minimum required

SCK rate for an application can be derived based on the sample

period (tCYC), the number of bits that must be read (including

data and optional status bits), and the digital interface mode

being used. Timing diagrams and explanations for each digital

interface mode are given in the digital modes of operation sections

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