AD4011 datasheet(23/38 Pages) AD

23 / 38 page

Data Sheet

AD4003/AD4007/AD4011

Rev. B | Page 23 of 38

channels are switched. Switch the multiplexer channels imme-

diately after tQUIET1 has elapsed from the start of the conversion

to maximize settling time while preventing corruption of the

conversion result. To avoid conversion corruption, do not

switch the channels during the tQUIET1 time. If the analog inputs

are multiplexed during the quiet conversion time (tQUIET1), the

current conversion may be corrupted.

EASE OF DRIVE FEATURES

Input Span Compression

In single-supply applications, it is desirable to use the full range

of the ADC; however, the amplifier can have some headroom and

footroom requirements, which can be a problem, even if it is a

rail-to-rail input and output amplifier. The AD4003/AD4007/

AD4011 include a span compression feature, which increases

the headroom and footroom available to the amplifier by reducing

the input range by 10% from the top and bottom of the range

while still accessing all available ADC codes (see Figure 42). The

SNR decreases by approximately 1.9 dB (20 × log(8/10)) for the

reduced input range when span compression is enabled. Span

compression is disabled by default but can be enabled by writing to

the relevant register bit (see the Digital Interface section).

ADC

VREF = 4.096V

DIGITAL OUTPUT

ALL 2N

CODES

+FSR

–FSR

90% OF VREF = 3.69V

10% OF VREF = 0.41V

ANALOG

INPUT

IN+/IN–

Figure 42. Span Compression

High-Z Mode

The AD4003/AD4007/AD4011 incorporate high-Z mode, which

reduces the nonlinear charge kickback when the capacitor DAC

switches back to the input at the start of acquisition. Figure 43

shows the input current of the AD4003/AD4007/AD4011 with

high-Z mode enabled and disabled. The low input current makes

the ADC easier to drive than the traditional SAR ADCs available in

the market, even with high-Z mode disabled. The input current

reduces further to submicroampere range when high-Z mode is

enabled. The high-Z mode is disabled by default but can be enabled

by writing to the register (see Table 14). Disable high-Z mode for

input frequencies above 100 kHz or when multiplexing.

–15

–12

–9

–6

–3

–5

–4

–3

–2

–1

0123

INPUT DIFFERENTIAL VOLTAGE (V)

HIGH-Z DISABLED, 2MSPS

HIGH-Z DISABLED, 1MSPS

HIGH-Z DISABLED, 500kSPS

HIGH-Z ENABLED, 2MSPS

HIGH-Z ENABLED, 1MSPS

HIGH-Z ENABLED, 500kSPS

Figure 43. Input Current vs. Input Differential Voltage, VDD = 1.8 V

VIO = 3.3 V, VREF = 5 V, 25°C

To achieve the optimum data sheet performance from high

resolution precision SAR ADCs, system designers are often

forced to use a dedicated high power, high speed amplifier to

drive the traditional switched capacitor SAR ADC inputs for

their precision applications, which is commonly encountered in

designing a precision data acquisition signal chain. The benefits

of high-Z mode are low input current for slow (<10 kHz) or dc

type signals and improved distortion (THD) performance over

a frequency range of up to 100 kHz. High-Z mode allows a

choice of lower power and lower bandwidth precision amplifiers

with a lower RC filter cutoff to drive the ADC, removing the need

for dedicated high speed ADC drivers, which saves system power,

size, and cost in precision, low bandwidth applications. High-Z

mode allows the amplifier and RC filter in front of the ADC to be

chosen based on the signal bandwidth of interest and not based

on the settling requirements of the switched capacitor SAR ADC

inputs.

Additionally, the AD4003/AD4007/AD4011 can be driven with a

much higher source impedance than traditional SARs, which

means the resistor in the RC filter can have a value 10 times larger

than previous SAR designs and, with high-Z mode enabled, can

tolerate even larger impedance. Figure 44 shows the THD per-

formance for various source impedances with high-Z mode

disabled and enabled.

AD4011 Datasheet(PDF) 23 Page - Analog Devices

AD4011 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL