AD9628 datasheet(37/43 Pages) AD

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AD9628

Data Sheet

Rev. C | Page 36 of 42

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 18 are not currently supported for this device.

Table 18. Memory Map Registers

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Comments

Chip Configuration Registers

0x00

SPI port

config

(global)

Open

LSB first

Soft reset

LSB first

Open

0x18

The nibbles

are mirrored

so LSB-first

mode or

MSB-first

mode

registers

correctly,

regardless of

shift mode

0x01

Chip ID

(global)

8-bit chip ID[7:0]

AD9628 = 0x89

Read

only

Unique Chip

ID used to

differentiate

devices; read

only

0x02

Chip grade

(global)

Open

Speed grade ID

100 = 105 MSPS

101 = 125 MSPS

Open

Read

only

Unique

speed grade

ID used to

differentiate

devices; read

only

Channel Index and Transfer Registers

0x05

Device

index

(global)

Open

Data

Channel B

Data

Channel A

0x03

Bits are set

to determine

which device

on the chip

receives the

next write

command;

applies to

local

registers

only

0xFF

Transfer

(global)

Open

Transfer

0x00

Synchron-

ously

transfers

data from

the master

shift register

to the slave

ADC Functions

0x08

Power

modes

(local)

Open

External

power-

downpin

function

0 = PDWN

1=standby

Open

Internal power-down mode

00 = normal operation

01 = full power-down

10 = standby

11 = digital reset

0x00

Determines

various

generic

modes of

chip

operation

0x09

Global

clock

(global)

Open

Duty cycle

stabilizer

0 =

disabled

1 =

enabled

0x01

0x0B

Clock

divide

(global)

Open

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

The divide

ratio is value

plus 1

AD9628 Datasheet(PDF) 37 Page - Analog Devices

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