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Data Sheet

AD9628

Rev. C | Page 41 of 42

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9628 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements that are needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9628, it is recommended that

two separate 1.8 V supplies be used. Use one supply for analog

(AVDD); use a separate supply for the digital outputs (DRVDD).

For both AVDD and DRVDD, several different decoupling capa-

citors should be used to cover both high and low frequencies.

Place these capacitors close to the point of entry at the PCB level

and close to the pins of the part, with minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9628. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

LVDS Operation

The AD9628 defaults to CMOS output mode on power-up.

If LVDS operation is desired, this mode must be programmed,

using the SPI configuration registers after power-up. When the

AD9628 powers up in CMOS mode with LVDS termination

resistors (100 Ω) on the outputs, the DRVDD current can be

higher than the typical value until the part is placed in LVDS

mode. This additional DRVDD current does not cause damage

to the AD9628, but it should be taken into account when consid-

ering the maximum DRVDD current for the part.

To avoid this additional DRVDD current, the AD9628 outputs

can be disabled at power-up by taking the PDWN pin high.

After the part is placed into LVDS mode via the SPI port, the

PDWN pin can be taken low to enable the outputs.

Clock Stability Considerations

When powered on, the AD9628 enters an initialization phase

during which an internal state machine sets up the biases and

the registers for proper operation. During the initialization

process, the AD9628 needs a stable clock. If the ADC clock

source is not present or not stable during ADC power-up, it

disrupts the state machine and causes the ADC to start up in an

unknown state. To correct this, an initialization sequence must

be reinvoked after the ADC clock is stable by issuing a digital

reset via Register 0x08. In the default configuration (internal

VREF, ac-coupled input) where VREF and VCM are supplied by the

ADC itself, a stable clock during power-up is sufficient. In the

case where VREF and/or VCM are supplied by an external source,

these, too, must be stable at power-up; otherwise, a subsequent

digital reset via Register 0x08 is needed. Interruption of the

sample clock during operation and changes in sample rate also

necessitate a digital reset.

The pseudo code sequence for a digital reset is as follows:

SPI_Write (0x08, 0x03);

# Digital Reset

SPI_Write (0x08, 0x00);

# Can be asserted

as soon as the next SPI cycle, normal

operation resumes after 2.9e6 sample clock

cycles, ADC outputs 0s until the reset is

complete.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. A continuous, exposed

(no solder mask) copper plane on the PCB should mate to the

AD9628 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged to

prevent solder wicking through the vias, which can compromise

the connection.

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP).

VCM

The VCM pin should be decoupled to ground with a 0.1 μF

capacitor.

Reference Decoupling

The VREF pin should be externally decoupled to ground with

a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF

ceramic capacitor.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9628 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

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