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Data Sheet

AD9634

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 57, the power dissipated by the AD9634 is

proportional to its sample rate. The data in Figure 57 was taken

using the same operating conditions as those used for the Typical

Performance Characteristics section.

0.4

0.3

0.2

0.1

0.25

0.20

0.15

0.10

0.05

85 100 115 130 145 160 175 190 205 220 235 250

ENCODE FREQUENCY (MSPS)

TOTAL POWER

IAVDD

IDRVDD

Figure 57. AD9634-250 Power and Current vs. Sample Rate

By setting the internal power-down mode bits (Bits[1:0]) in the

power modes register (Address 0x08) to 01, the AD9634 is placed

in power-down mode. In this state, the ADC typically dissipates

5 mW. During power-down, the output drivers are placed in a

high impedance state.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to

normal operation. As a result, wake-up time is related to the

time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. To put the part into standby

mode, set the internal power-down mode bits (Bits[1:0]) in the

power modes register (Address 0x08) to 10. See the Memory

Map section and AN-877 Application Note, Interfacing to High

Speed ADCs via SPI for additional details.

DIGITAL OUTPUTS

The AD9634 output drivers can be configured for either ANSI

LVDS or reduced swing LVDS using a 1.8 V DRVDD supply.

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI

control.

Digital Output Enable Function (OEB)

The AD9634 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled using the SPI interface.

The data outputs can be three-stated by using the output enable

bar bit (Bit 4) in Register 0x14. This OEB function is not intended

for rapid access to the data bus.

Timing

The AD9634 provides latched data with a pipeline delay of 10 input

sample clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines as well as the loads

placed on these lines to reduce transients within the AD9634.

These transients may degrade converter dynamic performance.

The lowest typical conversion rate of the AD9634 is 40 MSPS. At

clock rates below 40 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9634 also provides the data clock output (DCO) intended

for capturing the data in an external register. Figure 2 shows

timing diagram of the AD9634 output modes.

ADC OVERRANGE (OR)

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipeline and, therefore, is

subject to a latency of 10 ADC clock cycles. An overrange at the

input is indicated by this bit 10 clock cycles after it occurs.

Table 10. Output Data Format

Input (V)

VIN+ − VIN−, Input Span = 1.75 V p-p (V)

Offset Binary Output Mode

Twos Complement Mode (Default)

VIN+ − VIN−

< −0.875

0000 0000 0000

1000 0000 0000

VIN+ − VIN−

= −0.875

0000 0000 0000

1000 0000 0000

VIN+ − VIN−

= 0

1000 0000 0000

0000 0000 0000

VIN+ − VIN−

= +0.875

1111 1111 1111

0111 1111 1111

VIN+ − VIN−

> +0.875

1111 1111 1111

0111 1111 1111

Rev. B | Page 23 of 30

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