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Data Sheet

AD9212

Rev. E | Page 23 of 56

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9212 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional biasing.

Figure 51 shows the preferred method for clocking the AD9212.

The low jitter clock source is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9212 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9212, and it preserves the

fast rise and fall times of the signal, which are critical to low

jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

CLK+

50Ω

100Ω

CLK–

CLK+

ADC

AD9212

Mini-Circuits®

ADT1–1WT, 1:1Z

XFMR

Figure 51. Transformer-Coupled Differential Clock

Another option is to ac-couple a differential PECL signal to the

sample clock input pins as shown in Figure 52. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515 family of clock

drivers offers excellent jitter performance.

100Ω

0.1µF

240Ω

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

50Ω1

CLK

150Ω RESISTORS ARE OPTIONAL.

CLK–

CLK+

ADC

AD9212

PECL DRIVER

CLK+

CLK–

Figure 52. Differential PECL Sample Clock

100Ω

0.1µF

50Ω1

LVDS DRIVER

50Ω1

CLK

150Ω RESISTORS ARE OPTIONAL.

CLK–

CLK+

ADC

AD9212

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

CLK+

CLK–

Figure 53. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be driven directly from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 54). Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages of up to 3.3 V, making the

selection of the drive logic voltage very flexible.

0.1µF

39kΩ

CMOS DRIVER

50Ω1

OPTIONAL

100Ω

0.1µF

CLK

150Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9212

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

CLK+

Figure 54. Single-Ended 1.8 V CMOS Sample Clock

0.1µF

CMOS DRIVER

50Ω1

OPTIONAL

100Ω

CLK

150Ω RESISTOR IS OPTIONAL.

0.1µF

CLK–

CLK+

ADC

AD9212

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

CLK+

Figure 55. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9212 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9212. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. However,

some applications may require the DCS function to be off. If so,

keep in mind that the dynamic range performance can be affected

when operated in this mode. See the Memory Map section for

more details on using this feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately eight clock cycles

to allow the DLL to acquire and lock to the new rate.

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