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AD9445 Datasheet(PDF) 1 Page - Analog Devices |
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AD9445 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 41 page  14-Bit, 105/125 MSPS, IF Sampling ADC AD9445 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. FEATURES 125 MSPS guaranteed sampling rate (AD9445BSV-125) 78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p) 74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p) 77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p) 74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p) 73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p) 102 dBFS 2-tone SFDR with 30 MHz and 31 MHz 92 dBFS 2-tone SFDR with 170 MHz and 171 MHz 60 fsec rms jitter Excellent linearity DNL = ±0.25 LSB typical INL = ±0.8 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output clock available 3.3 V and 5 V supply operation APPLICATIONS Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Medical imaging Communications instrumentation GENERAL DESCRIPTION The AD9445 is a 14-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip IF sampling track-and-hold circuit. It is optimized for performance, small size, and ease of use. The product operates at up to a 125 MSPS conversion rate and is designed for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. FUNCTIONAL BLOCK DIAGRAM CMOS OR LVDS OUTPUT STAGING CLOCK AND TIMING MANAGEMENT AGND DRGND DRVDD VREF CLK+ VIN+ AD9445 VIN– CLK– DCO AVDD1 AVDD2 DCS MODE DFS RF ENABLE OUTPUT MODE T/H BUFFER 14 PIPELINE ADC 2 28 2 OR D13 TO D0 REF REFB SENSE REFT Figure 1. Optional features allow users to implement various selectable operating conditions, including input range, data format select, high IF sampling mode, and output data mode. The AD9445 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range −40°C to +85°C. PRODUCT HIGHLIGHTS 1. High performance: outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers. 2. Ease of use: on-chip reference and high input impedance track-and-hold with adjustable analog input range and an output clock simplifies data capture. 3. Packaged in a Pb-free, 100-lead TQFP/EP package. 4. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths. 5. OR (out-of-range) outputs indicate when the signal is beyond the selected input range. 6. RF enable pin allows users to configure the device for optimum SFDR when sampling frequencies above 210 MHz (AD9445-125) or 240 MHz (AD9445-105). |
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