AD9445 datasheet(28/41 Pages) AD

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AD9445

Rev. 0 | Page 27 of 40

INPUT FREQUENCY (MHz)

1000

100

0.2ps

0.5ps

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic

performance, including both SFDR and SNR, is maximized

when the AD9445 is used in LVDS mode; designers are

encouraged to take advantage of this mode. The AD9445

outputs include complimentary LVDS outputs for each data bit

(Dx+/Dx−), the overrange output (OR+/OR−), and the output

data clock output (DCO+/DCO−). The RSET resistor current is

multiplied on-chip, setting the output current at each output

equal to a nominal 3.5 mA (11 × IR

SET). A 100 Ω differential

termination resistor placed at the LVDS receiver inputs results

in a nominal 350 mV swing at the receiver. LVDS mode

facilitates interfacing with LVDS receivers in custom ASICs and

FPGAs that have LVDS capability for superior switching

performance in noisy environments. Single point-to-point net

topologies are recommended, with a 100 Ω termination resistor

placed as close to the receiver as possible. It is recommended to

keep the trace length less than 2 inches and to keep differential

output trace lengths as equal as possible.

Figure 66. SNR vs. Input Frequency and Jitter

POWER CONSIDERATIONS

Care should be taken when selecting a power source. The use of

linear dc supplies is highly recommended. Switching supplies

tend to have radiated components that may be received by the

AD9445. Each of the power supply pins should be decoupled as

closely to the package as possible using 0.1 μF chip capacitors.

CMOS Mode

In applications that can tolerate a slight degradation in dynamic

performance, the AD9445 output drivers can be configured to

interface with 2.5 V or 3.3 V logic families by matching

DRVDD to the digital supply of the interfaced logic. CMOS

outputs are available when OUTPUT MODE is CMOS logic

low (or AGND for convenience). In this mode, the output data

bits, Dx, are single-ended CMOS, as is the overrange output,

OR. The output clock is provided as a differential CMOS signal,

DCO+/DCO−. Lower supply voltages are recommended to

avoid coupling switching transients back to the sensitive analog

sections of the ADC. The capacitive load to the CMOS outputs

should be minimized, and each output should be connected to a

single gate through a series resistor (220 Ω) to minimize

switching transients caused by the capacitive loading.

The AD9445 has separate digital and analog power supply pins.

The analog supplies are denoted AVDD1 (3.3 V) and AVDD2

(5 V), and the digital supply pins are denoted DRVDD. Although

the AVDD1 and DRVDD supplies can be tied together, best

performance is achieved when the supplies are separate. This is

because the fast digital output swings can couple switching

current back into the analog supplies. Note that both AVDD1

and AVDD2 must be held within 5% of the specified voltage.

The DRVDD supply of the AD9445 is a dedicated supply for the

digital outputs in either LVDS or CMOS output mode. When in

LVDS mode, the DRVDD should be set to 3.3 V. In CMOS

mode, the DRVDD supply can be connected from 2.5 V to

3.6 V for compatibility with the receiving logic.

TIMING

The AD9445 provides latched data outputs with a pipeline delay

of 13 clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of CLK+. Refer to

DIGITAL OUTPUTS

LVDS Mode

Figure 2 and

Figure 3 for detailed timing diagrams.

The off-chip drivers on the chip can be configured to provide

LVDS-compatible output levels via Pin 3 (OUTPUT MODE).

LVDS outputs are available when OUTPUT MODE is CMOS

logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET

AD9445 Datasheet(PDF) 28 Page - Analog Devices

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