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AD9865

Data Sheet

Rev. B | Page 36 of 48

1.0V

ADCs

REFT

REFB

0.1

µF

0.1

µF

0.1

µF

TOP

VIEW

Figure 75. ADC Reference and Decoupling

The ADC has an internal voltage reference and reference ampli-

fier as shown in Figure 75. The internal band gap reference

generates a stable 1 V reference level that is converted to a dif-

ferential 1 V reference centered about mid-supply (AVDD/2).

The outputs of the differential reference amplifier are available

at the REFT and REFB pins and must be properly decoupled for

optimum performance. The REFT and REFB pins are conven-

iently situated at the corners of the CSP package such that C1

(0603 type) can be placed directly across its pins. C3 and C4 can

be placed underneath C1, and C2 (10 µF tantalum) can be

placed furthest from the package.

Table 22. SPI Registers for Rx ADC

Address (Hex)

Bit

Description

0x04

(5)

Duty cycle restore circuit

(4)

ADC clock from PLL

0x07

(4)

ADC low power mode

0x13

(2:0)

ADC power bias adjust

AGC TIMING CONSIDERATIONS

When implementing a digital AGC timing loop, it is important

to consider the Rx path latency and settling time of the Rx path

in response to a change in gain setting. Figure 21 and Figure 24

show the RxPGA’s settling response to a 60 dB and 5 dB change

in gain setting when using the Tx[5:0] or PGA[5:0] port. While

the RxPGA settling time may also show a slight dependency on

the LPF’s cut-off frequency, the ADC’s pipeline delay along with

the ADIO bus interface presents a more significant delay. The

amount of delay or latency is dependent on whether a half-or

full-duplex is selected. An impulse response at the RxPGA’s

input can be observed after 10.0 ADC clock cycles (1/fADC) in

the case of a half-duplex interface, and 10.5 ADC clock cycles in

the case of a full-duplex interface. This latency, along with the

RxPGA settling time, should be considered to ensure stability of

the AGC loop.

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