AD9865

Data Sheet

Rev. B | Page 6 of 48

Parameter

Temp

Test Level

Min

Typ

Max

Unit

Tx Mode

25°C

IV

112

130

mA

25°C

IV

46

49.5

mA

Rx Mode

25°C

IV

225

253

mA

25°C

IV

36.5

39

mA

RxPGA and LPF

25°C

III

87

mA

ADC

25°C

III

108

mA

TxDAC

25°C

III

38

mA

IAMP (Programmable)

25°C

III

10

120

mA

Reference

25°C

III

170

mA

CLK PLL and Synthesizer

25°C

III

107

mA

MAXIMUM ALLOWABLE POWER DISSIPATION

Full

IV

1.66

W

STANDBY POWER CONSUMPTION

IS_TOTAL (Total Supply Current)

Full

13

mA

POWER DOWN DELAY (USING PWR_DWN PIN)

RxPGA and LPF

25°C

III

440

ns

ADC

25°C

III

12

ns

TxDAC

25°C

III

20

ns

IAMP

25°C

III

20

ns

CLK PLL and synthesizer

25°C

III

27

ns

POWER UP DELAY (USING PWR_DWN PIN)

RxPGA and LPF

25°C

III

7.8

µs

ADC

25°C

III

88

ns

TxDAC

25°C

III

13

µs

IAMP

25°C

III

20

ns

CLK PLL and Synthesizer

25°C

III

20

µs

1

Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent.

2

Default power-up settings for MODE = LOW and CONFIG = LOW.

DIGITAL SPECIFICATIONS

Table 4.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

CMOS LOGIC INPUTS

High Level Input Voltage

Full

VI

DRVDD – 0.7

V

Low Level Input Voltage

Full

VI

0.4

V

Input Leakage Current

12

µA

Input Capacitance

Full

VI

3

pF

Full

VI

DRVDD – 0.7

V

Full

VI

0.4

V

Full

VI

1.5/2.3

ns

Full

VI

1.9/2.7

ns

Full

VI

0.7/0.7

ns

Full

VI

1.0/1.0

ns

RESET

1

Clock

cycles