AD9865 datasheet(32/49 Pages) AD

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Data Sheet

AD9865

Rev. B | Page 31 of 48

transformer1 should be specified to handle the dc standing

current, IBIAS, drawn by the IAMP. Also, because IBIAS remains

signal independent, a series resistor (not shown) can be inserted

between AVDD and the transformer’s center-tap to reduce the

IAMP’s common-mode voltage, VCM, and reduce the power

dissipation on the IC. The VCM bias should not exceed 5.0 V and

the power dissipated in the IAMP alone is as follows:

PIAMP = 2 × (N + G) × I × VCM

(2)

TxDAC

IOUTN–

IOUTN+

IOUTG–

IOUTG+

0 TO –7.5dB

0 TO –12dB

IAMP

RSET

0.1

µF

AVDD

0.1

µF

IBIAS = 2 × (N+G) × 1

IOUTPK

T:1

IOUTPK = (N+G) × 1

P_OUTPK = (IOUTPK)2 × T2 × RL

Figure 64. Current-Mode Operation

A step-down transformer1 with a turn ratio, T, can be used to

increase the output power, P_OUT, delivered to the load. This

causes the output load, RL, to be reflected back to the IAMP’s

differential output by T2, resulting in a larger differential voltage

swing seen at the IAMP’s output. For example, the IAMP can

deliver 24 dBm of peak power to a 50 Ω load, if a 1.41:1 step-

down transformer is used. This results in 5 V p-p voltage swings

appearing at IOUTN+ and IOUTN− pins. Figure 42 shows how

the third order intercept point, OIP3, of the IAMP varies as a

function of common-mode voltage over a 2.5 MHz to 20.0 MHz

span with a 2-tone signal having a peak power of approximately

24 dBm with IOUTPK = 50 mA.

For applications requiring an IOUTPK exceeding 50 mA, set the

secondary’s path to deliver the additional current to the load.

IOUTG+ and IOUTN+ should be shorted as well as IOUTG−

and IOUTN−. If IOUTPK represents the peak current to be

delivered to the load, then the current gain in the secondary

path, G, can be set by the following equation:

G = IOUTPK/12.5 − 4

(3)

The linearity performance becomes limited by the secondary

mirror path’s distortion.

The B6080 and BX6090 transformers from Pulse Engineering are worthy of

consideration for current and voltage modes.

IAMP VOLTAGE-MODE OPERATION

The voltage-mode configuration is shown in Figure 65. This

configuration is suited for applications having a poorly defined

load that can vary over a considerable range. A low impedance

voltage driver can be realized with the addition of two external

RF bipolar npn transistors (Phillips PBR951) and resistors. In

this configuration, the current mirrors in the primary path

(IOUTN outputs) feed into scaling resistors, R, generating a

differential voltage into the bases of the npn transistors. These

transistors are configured as source followers with the secon-

dary path current mirrors appearing at IOUTG+ and IOUTG−

providing a signal-dependent bias current. Note that the

IOUTP outputs must remain open for proper operation.

IOUTN–

IOUTN+

IOUTG–

IOUTG+

0 TO –7.5dB

0 TO –12dB

RSET

0.1

µF

TO LOAD

AVDD

IOUTPK

AVDD

RS 0.1µF

RS 0.1

µF

DUAL NPN

PHILLIPS PBR951

IAMP

TxDAC

Figure 65. Voltage-Mode Operation

The peak differential voltage signal developed across the npn’s

bases is as follows:

VOUTPK = R × (N × I)

(4)

where:

N is the gain setting of the primary mirror.

I is the standing current of the TxDAC defined in Equation 1.

The common-mode bias voltage seen at IOUTN+ and IOUTN−

is approximately AVDD − VOUTPK, while the common-mode

voltage seen at IOUTG+ and IOUTG− is approximately the

npn’s VBEdrop below this level (AVDD − VOUTPK − 0.65). In

the voltage-mode configuration, the total power dissipated

within the IAMP is as follows :

PIAMP = 2 × I × {(AVDD − VOUTPK) × N

+ (AVDD − VOUTPK − 0.65) × G}

(5)

The emitters of the npn transistors are ac-coupled to the trans-

former1 via a 0.1 µF blocking capacitor and series resistor of 1 Ω

to 2 Ω. Note that protection diodes are not shown for clarity

purposes, but should be considered if interfacing to a power or

phone line.

The amount of standing and signal-dependent current used to

bias the npn transistors depends on the peak current, IOUTPK,

required by the load. If the load is variable, determine the worst

case, IOUTPK, and add 3 mA of margin to ensure that the npn

transistors remain in the active region during peak load

currents. The gain of the secondary path, G, and the TxDAC’s

standing current, I, can be set using the following equation:

IOUTPK + 3 mA = G × I

(6)

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