Electronic Components Datasheet Search
  English  ▼

X  

SLG46170 Datasheet(PDF) 42 Page - Dialog Semiconductor

Part # SLG46170
Description  Personal Computers and Servers
PDF  87 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

SLG46170 Datasheet(HTML) 42 Page - Dialog Semiconductor

Back Button SLG46170 Datasheet HTML 38Page - Dialog Semiconductor SLG46170 Datasheet HTML 39Page - Dialog Semiconductor SLG46170 Datasheet HTML 40Page - Dialog Semiconductor SLG46170 Datasheet HTML 41Page - Dialog Semiconductor SLG46170 Datasheet HTML 42Page - Dialog Semiconductor SLG46170 Datasheet HTML 43Page - Dialog Semiconductor SLG46170 Datasheet HTML 44Page - Dialog Semiconductor SLG46170 Datasheet HTML 45Page - Dialog Semiconductor SLG46170 Datasheet HTML 46Page - Dialog Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 42 / 87 page
background image
000-0046170-103
Page 41 of 86
SLG46170
Each Macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by reg<575:572>
10.1.2 2-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings
10.2 3-Bit LUT or Pipe Delay Macrocell
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay.
When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a
single output, which goes back into the connection matrix.
When used as a pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). The pipe
delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. The first delay option (ONE PIPE OUT)
is fixed at the output of the first flip-flop stage. The other two outputs (OUT0 and OUT1) provide user selectable options for 1 –
16 stages of delay. There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input mux that is controlled
by reg <664:661> for OUT0 and reg <668:665> for OUT1. The 4-input mux is used to control the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG46170 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the RC Oscillator within the SLG46722). The sum of the number of DFF cells used will
be the total time delay of the Pipe Delay logic cell.
Table 44. DFF4 Register Settings
Signal Function
Register Bit
Address
Register Definition
LUT2_0 or DFF4
Select
596
0: LUT2_0
1: DFF4
DFF4 or Latch
Select
572
0: DFF function
1: Latch function
DFF4 Output Select
573
0: Q output
1: nQ output
DFF4 Initial Polarity
Select
574
0: Low
1: High



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com