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SLG46170 Datasheet(PDF) 63 Page - Dialog Semiconductor |
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SLG46170 Datasheet(HTML) 63 Page - Dialog Semiconductor |
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63 / 87 page ![]() 000-0046170-103 Page 62 of 86 SLG46170 14.3 Programmable Delay Register Settings Table 55. Programmable Delay Register Settings Signal Function Register Bit Address Register Definition Delay value select for programmable delay & edge detector (VDD = 3.3V, typical condition) reg<1001:1000> 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns Select the edge mode of programmable delay & edge detector reg<1003:1002> 00: Rising Edge Detector 01: Falling Edge Detector 10: Both Edge Detector 11: Both Edge Delay Select edge detector output mode reg<1004> 0: Edge Detector Output 1: Delayed Edge Detector Output |
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