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SLG46170 Datasheet(PDF) 32 Page - Dialog Semiconductor |
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SLG46170 Datasheet(HTML) 32 Page - Dialog Semiconductor |
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32 / 87 page ![]() 000-0046170-103 Page 31 of 86 SLG46170 8.2 Matrix Output Table Table 24. Matrix Output Table Register Bit Address Matrix Output Signal Function Matrix Output Number reg<5:0> Reserved 0 reg<11:6> Matrix Out: PIN3 Digital Output Source 1 reg<17:12> Matrix Out: PIN4 Digital Output Source 2 reg<23:18> Matrix Out: PIN5 Digital Output Source 3 reg<29:24> Matrix Out: PIN6 Digital Output Source 4 reg<35:30> Reserved 5 reg<41:36> Matrix Out: PIN6 Digital Output Source 6 reg<47:42> Matrix Out: PIN8 Digital Output Source (4X Drive) 7 reg<53:48> Matrix Out: Input for Delay0 or Counter0 External Clock 8 reg<59:54> Matrix Out: Input for Delay1 or Counter1 Reset Input 9 reg<65:60> Matrix Out: Input for Counter1 External Clock or Delay1 External Clock 10 reg<71:66> Matrix Out: Input for Delay2 or Counter2 Reset Input 11 reg<77:72> Matrix Out: Input for Counter2 External Clock or Delay2 External Clock 12 reg<83:78> Matrix Out: Input for Delay3 or Counter3 Reset Input 13 reg<89:84> Matrix Out: Input for Counter3 External Clock or Delay3 External Clock 14 reg<95:90> Matrix Out: Input for Delay4 or Counter4 External Clock 15 reg<101:96> Matrix Out: Input for Delay5 or Counter5 External Clock 16 reg<107:102> Matrix Out: Input for Delay6 or Counter6 External Clock 17 reg<113:108> Matrix Out: Input for Delay7 or Counter7 External Clock 18 reg<119:114> Matrix Out: Clock Input of DFF0 19 reg<125:120> Matrix Out: Data Input of DFF0 20 reg<131:126> Matrix Out: nRST (nSET) of DFF0 21 reg<137:132> Matrix Out: Clock Input of DFF1 22 reg<143:138> Matrix Out: Data Input of DFF1 23 reg<149:144> Matrix Out: nRST (nSET) of DFF1 24 reg<155:150> Matrix Out: Clock Input of DFF2 25 reg<161:156> Matrix Out: Data Input of DFF2 26 reg<167:162> Matrix Out: nRST (nSET) of DFF2 27 reg<173:168> Matrix Out: Clock Input of DFF3 28 reg<179:174> Matrix Out: Data Input of DFF3 29 reg<185:180> Matrix Out: nRST (nSET) of DFF3 30 reg<191:186> Matrix Out: Clock Input of DFF5 31 reg<197:192> Matrix Out: Data Input of DFF5 32 reg<203:198> Matrix Out: Clock Input of DFF6 33 reg<209:204> Matrix Out: Data Input of DFF6 34 reg<215:210> Matrix Out: In0 of LUT4_0 35 reg<221:216> Matrix Out: In1 of LUT4_0 36 |
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