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SLG46170 Datasheet(PDF) 59 Page - Dialog Semiconductor |
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SLG46170 Datasheet(HTML) 59 Page - Dialog Semiconductor |
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59 / 87 page ![]() 000-0046170-103 Page 58 of 86 SLG46170 12.9 CNT/DLY7 Register Settings Table 54. CNT/DLY7 Register Settings Signal Function Register Bit Address Register Definition Counter/Delay67 Mode Select reg<824> 0: Delay Mode 1: Counter Mode Counter/Delay7 Clock Source Select (external clock is only for counter mode) reg<827:825> 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter 6 Overflow Counter6 Control Data/Delay7 Time Control reg<841:828> 1-16384: (delay time = (counter control data +2) /freq) Delay7 Mode Select reg<843:842> 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges |
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