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SLG46170 Datasheet(PDF) 70 Page - Dialog Semiconductor

Part # SLG46170
Description  Personal Computers and Servers
PDF  87 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

SLG46170 Datasheet(HTML) 70 Page - Dialog Semiconductor

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000-0046170-103
Page 69 of 86
SLG46170
18.0 Appendix A - SLG46170 Register Definition
Register Bit
Address
Signal Function
Register Bit Definition
reg<5:0>
Reserved
reg<11:6>
Matrix Out
PIN3 Digital Output Source
reg<17:12>
Matrix Out
PIN4 Digital Output Source
reg<23:18>
Matrix Out
PIN5 Digital Output Source
reg<29:24>
Matrix Out
PIN6 Digital Output Source
reg<35:30>
Reserved
reg<41:36>
Matrix Out
PIN7 Digital Output Source
reg<47:42>
Matrix Out
PIN8 Digital Output Source (4X Drive)
reg<53:48>
Matrix Out
Input for delay0 or Counter0 external clock
reg<59:54>
Matrix Out
Input for delay1 or counter1 reset input
reg<65:60>
Matrix Out
Input for Counter1 external clock or delay1 external
clock
reg<71:66>
Matrix Out
Input for delay2 or counter2 reset input
reg<77:72>
Matrix Out
Input for Counter2 external clock or delay2 external
clock
reg<83:78>
Matrix Out
Input for delay3 or counter3 reset input
reg<89:84>
Matrix Out
Input for Counter3 external clock or delay3 external
clock
reg<95:90>
Matrix Out
Input for delay4 or Counter4 external clock
reg<101:96>
Matrix Out
Input for delay5 or Counter5 external clock
reg<107:102> Matrix Out
Input for delay6 or Counter6 external clock
reg<113:108>
Matrix Out
Input for delay7 or Counter7 external clock
reg<119:114>
Matrix Out
Clock Input of DFF0
reg<125:120> Matrix Out
Data Input of DFF0
reg<131:126> Matrix Out
nRST (nSET) of DFF0
reg<137:132> Matrix Out
Clock Input of DFF1
reg<143:138> Matrix Out
Data Input of DFF1
reg<149:144> Matrix Out
nRST (nSET) of DFF1
reg<155:150> Matrix Out
Clock Input of DFF2
reg<161:156> Matrix Out
Data Input of DFF2
reg<167:162> Matrix Out
nRST (nSET) of DFF2
reg<173:168> Matrix Out
Clock Input of DFF3
reg<179:174> Matrix Out
Data Input of DFF3
reg<185:180> Matrix Out
nRST (nSET) of DFF3
reg<191:186> Matrix Out
Clock Input of DFF5
reg<197:192> Matrix Out
Data Input of DFF5
reg<203:198> Matrix Out
Clock Input of DFF6
reg<209:204> Matrix Out
Data Input of DFF6
reg<215:210> Matrix Out
In0 of LUT4_0
reg<221:216> Matrix Out
In1 of LUT4_0
reg<227:222> Matrix Out
In2 of LUT4_0



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