DA9213 datasheet(53/62 Pages) DIALOG

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Multi-Phase 5A/Phase DC-DC Buck Converter

Datasheet

Revision 2.2

23-Oct-2017

CFR0011-120-00

53 of 62

Bit

Type

Label

Description

R/W

CPHA

4-WIRE interface clock phase (see Table 10)

R/W

CPOL

4-WIRE interface clock polarity

0: SK is low during idle

1: SK is high during idle

R/W

nCS_POL

4-WIRE chip select polarity

0: nCS is low active

1: nCS is high active

Bit

Type

Label

Description

0x106

INTERFACE2

R/W

IF_TYPE

0: Power manager interface is 4-WIRE. Automatically

configures GPIO3 and GPI4 as interface signals. The

GPIO configuration is overruled.

1: Power manager interface is 2-WIRE

R/W

PM_IF_HSM

Enables continuous high speed mode on 2-WIRE

interface if asserted (no master code required)

R/W

PM_IF_FMP

Enables 2-WIRE interface operating with fast mode+

timings if asserted

R/W

PM_IF_V

0: Power manager interface in 2-WIRE mode is

supplied from VDDCORE (4-WIRE always from

VDDIO)

1: Power manager interface in 2-WIRE mode is

supplied from VDDIO (4-WIRE always from VDDIO)

0:3

R/W

(reserved)

8.1.4.2

OTP Fusing Registers

Bit

Type

Label

Description

0x140

OTP_CONT2

R/W

OTP_CONF_LO

0: Registers 0x54 to 0x5E and 0xD0 to 0xDA are not

locked for OTP programming (should be selected

for unmarked evaluation samples)

1: Registers 0x54 to 0x5E and 0xD0 to 0xDA are locked

in OTP (no further fusing possible)

R/W

OTP_APPS_LO

0: Registers 0x105, 0x106, 0x143 to 0x149 are not

locked for OTP programming (should be selected

for unmarked evaluation samples)

1: Registers 0x105, 0x106, 0x143 to 0x149 are locked

in OTP (no further fusing possible)

5:0

R/W

(reserved)

Bit

Type

Label

Description

0x141

OTP_ADDR

7:0

R/W

OTP_ADDR

OTP Array address

DA9213 Datasheet(PDF) 53 Page - Dialog Semiconductor

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