DA9213 datasheet(38/62 Pages) DIALOG

38 / 62 page

DA9213, DA9214, and DA9215

Multi-Phase 5A/Phase DC-DC Buck Converter

Datasheet

Revision 2.2

23-Oct-2017

CFR0011-120-00

38 of 62

SLAVEadr W A

REGadr

DATA

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = No Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

DATA

1-bit

8-bits

DATA

……….

8-bits

Repeated writes

Figure 28: 2-WIRE Page Write (SDA Line)

Via control WRITE_MODE an alternate write mode can be configured. Register addresses and data

are sent in alternation like in Figure 29 to support host repeated write operations that access several

non-consecutive registers. Data will be stored at the previously received register address.

An update of WRITE_MODE cannot be done without interruption within a transmission frame. Thus,

if not previously selected or not set as OTP default, the activation of Repeated Write must be done

with a regular write on WRITE_MODE followed by a stop condition. The next frame after a start

condition can be written in Repeated Write.

SLAVEadr W A

REGadr

DATA

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = No Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

REGadr

1-bit

8-bits

DATA

……….

8-bits

Repeated writes

Figure 29: 2-WIRE Repeated Write (SDA Line)

If a new START or STOP condition occurs within a message, the bus will return to IDLE mode.

DA9213 Datasheet(PDF) 38 Page - Dialog Semiconductor

DA9213 Datasheet(HTML) 38 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL