DA9213 datasheet(35/62 Pages) DIALOG

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DA9213, DA9214, and DA9215

Multi-Phase 5A/Phase DC-DC Buck Converter

Datasheet

Revision 2.2

23-Oct-2017

CFR0011-120-00

35 of 62

Table 11: 4-WIRE Interface Summary

Parameters

Signal lines

nCS

Chip select

SI Serial input data

Master out Slave in

SO Serial output data

Master in Slave out

Transmission clock

Interface

Push-pull with tristate

Supply voltage

Selected from VDDIO

1.6 V to 3.3 V

Data rate

Effective read/write data

Up to 7 Mbps

Transmission

Half-duplex

MSB first

16-bit cycles

7-bit address, 1-bit read/write, 8-bit data

Configuration

CPOL

Clock polarity

CPHA

Clock phase

nCS_POL

nCS is active low/high

Note 1

Reading the same register at high clock rates directly after writing it does not guarantee a correct

value. It is recommended to keep a delay of one frame until re-accessing a register that has just been

written (for example, by writing/reading another register address in-between).

7.4.2

2-WIRE Communication

The IF_TYPE bit in the INTERFACE2 register can be used to configure the DA9213, DA9214, and

DA9215 control interface as a 2-WIRE serial data interface. In this case the GPIO3 and GPI4 are

free for regular input/output functions. DA9213, DA9214, and DA9215 has a configurable device

write address (default: 0xD0) and a configurable device read address (default: 0xD1). See control

IF_BASE_ADDR1 for details of configurable addresses. The ADDR_SEL_CONF bit is used to

configure the device address as IF_BASE_ADDR1 or IF_BASE_ADDR2 depending on the voltage

level applied at a configurable GPI port (see Section 7.2.4).

The SK port functions as the 2-WIRE clock and the SI port carries all the power manager

bidirectional 2-WIRE data. The 2-WIRE interface is open-drain supporting multiple devices on a

single line. The bus lines have to be pulled HIGH by external pull-up resist

ors (in the 2 kΩ to 20 kΩ

range). The attached devices only drive the bus lines LOW by connecting them to ground. As a result

two devices cannot conflict if they drive the bus simultaneously. In standard/fast mode the highest

frequency of the bus is 400 kHz. The exact frequency can be determined by the application and does

not have any relation to the DA9213, DA9214, and DA9215 internal clock signals. DA9213, DA9214,

and DA9215 will follow the host clock speed within the described limitations, and does not initiate any

clock arbitration or slow down. An automatic interface reset can be triggered using control

2WIRE_TO if the clock signal stops to toggle for more than 35 ms.

The interface supports operation compatible to Standard, Fast, Fast-Plus and High Speed mode of

the I

2C-bus specification Rev 4. Operation in high speed mode at 3.4 MHz requires mode changing in

order to set spike suppression and slope control characteristics to be compatible with the I

2C-bus

specification. The high speed mode can be enabled on a transfer by transfer basis by sending the

master code (0000 1XXX) at the beginning of the transfer. DA9213, DA9214, and DA9215 do not

make use of clock stretching, and deliver read data without additional delay up to 3.4 MHz.

Alternatively, PM_IF_HSM configures the interface to use high speed mode continuously. In this

case, the master code is not required at the beginning of every transfer. This reduces the

communication overhead on the bus but limits the slaves attachable to the bus to compatible

devices.

DA9213 Datasheet(PDF) 35 Page - Dialog Semiconductor

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