S71PL254 datasheet(32/196 Pages) SPANSION

32 / 196 page

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

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I n f o rmation

Pin Description

Amax–A0

Address bus

DQ15–DQ0

16-bit data inputs/outputs/float

CE#

Chip Enable Inputs

OE#

Output Enable Input

WE#

Write Enable

VSS

Device Ground

Pin Not Connected Internally

RY/BY#

Ready/Busy output and open drain.

When RY/BY#= VIH, the device is ready to accept

read operations and commands. When RY/BY#=

VOL, the device is either executing an embedded

algorithm or the device is executing a hardware

reset operation.

WP#/ACC

Write Protect/Acceleration Input.

When WP#/ACC= VIL, the highest and lowest two

4K-word sectors are write protected regardless of

other sector protection configurations. When WP#/

ACC= VIH, these sector are unprotected unless the

DYB or PPB is programmed. When WP#/ACC= 12V,

program and erase operations are accelerated.

VIO

Input/Output Buffer Power Supply

(1.65 V to 1.95 V (for PL127J) or 2.7 V to 3.6 V (for

all PLxxxJ devices)

VCC

Chip Power Supply

(2.7 V to 3.6 V or 2.7 to 3.3 V)

RESET#

Hardware Reset Pin

CE#1

Chip Enable Inputs

Notes:

1. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J)

Logic Symbol

max+1

DQ15–DQ0

Amax–A0

CE#

OE#

WE#

RESET#

RY/BY#

WP#/ACC

VIO (VCCQ)

S71PL254 Datasheet(PDF) 32 Page - SPANSION

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