S71PL254 datasheet(74/196 Pages) SPANSION

74 / 196 page

S29PL127J/S29PL064J/S29PL032J for MCP

S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Advance

I n f o rmation

Write Operation Status

The device provides several bits to determine the status of a program or erase opera-

tion: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 19 and the following subsections describe

the function of these bits. DQ7 and DQ6 each offer a method for determining whether

a program or erase operation is complete or in progress. The device also provides a

Password Verify

(Notes 6, 8, 9)

555

2AA

555

PWA[0-3] PWD[0-3]

Password Unlock

(Notes 7, 10, 11) 7

555

2AA

555

PWA[0]

PWD[0]

PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3]

PPB Program

(Notes 5, 6, 12)

555

2AA

555

(SA)WP

RD(0)

PPB Status

555

2AA

555

(SA)WP

RD(0)

All PPB Erase

(Notes 5, 6, 13,

14)

555

2AA

555

(SA)

(SA)WP

RD(0)

PPB Lock Bit Set

555

2AA

555

PPB Lock Bit

Status (Note 15)

555

2AA

555

RD(1)

DYB Write (Note

555

2AA

555

DYB Erase (Note

555

2AA

555

DYB Status (Note

555

2AA

555

RD(0)

PPMLB Program

(Notes 5, 6, 12)

555

2AA

555

RD(0)

PPMLB Status

(Note 5)

555

2AA

555

RD(0)

SPMLB Program

(Notes 5, 6, 12)

555

2AA

555

RD(0)

SPMLB Status

(Note 5)

555

2AA

555

RD(0)

Table 18. Sector Protection Command Definitions

Legend:

DYB = Dynamic Protection Bit

OW = Address (A7:A0) is (00011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A7:A0) is

(00001010)

RD(0) = Read Data DQ0 for protection indicator bit.

RD(1) = Read Data DQ1 for PPB Lock status.

SA = Sector Address where security command applies. Address

bits Amax:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A7:A0) is

(00010010)

WP = PPB Address (A7:A0) is (00000010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

4. During unlock and command cycles, when lower address bits

are 555 or 2AAh as shown in table, address bits higher than

A11 (except where BA is required) and data bits higher than

DQ7 are don’t cares.

5. The reset command returns device to reading array.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6

validate bit has been fully programmed when DQ0 = 1. If

DQ0 = 0 in cycle 6, program command must be issued and

verified again.

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion

of password.

9. Command sequence returns FFh if PPMLB is set.

10. The password is written over four consecutive cycles, at

addresses 0-3.

11. A 2 µs timeout is required between any two portions of

password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have

been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6,

erase command must be issued and verified again. Before

issuing erase command, all PPBs should be programmed to

prevent PPB overerasure.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

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