CM6533DH datasheet(42/60 Pages) CMEDIA

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CM6533,CM6533N,CM6533X1,CM6533DH

USB Audio Chip

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Rev.1.6

4-3

R/W

frq_sel

SPI clock period

2’b00: by MCU clk div 4

2’b01: by MCU clk div 12

2’b10: by MCU clk div 16

2’b11: by MCU clk div 20

2’b0

(POR)

R/W

first_leading_bit

First data bit of 2-bit leading mode

1’b0(POR)

R/W

second_leading_bit Second data bit of 2-bit leading mode

1’b0(POR)

R/W

leading_bit_mode

RA8815 2-bit leading mode

0: No leading bits

1: 2-bit leading for each transaction

1’b0

(POR)

6.9.3

SPI Interrupt

Address: 3eh

Bits

R/W

Bit Mnemonic

Description

default

R/W

CPOL

Clock Polarity

1’b1(POR)

R/W

CPHA

Clock Phase

1’b1(POR)

5-4

R/W

CS_SEL

SPI CS Select

00: CS0

01: CS1

10: CS2(Default)

11: CS2

2’b10(POR)

slv_hid

SPI slave flag to HID interrupt

0: access to internal register

1: flag to HID interrupt

1’b0

(POR)

slv_rw

SPI slave read/write flag

0: read

1: write

1’b0

(POR)

R/W

slv_int_en

SPI slave interrupt

0: no interrupt

1: interrupt (Default)

Ext MCU can program this bit to make slave

mode interrupt

1’b1

(POR)

R/W

mst_int_en

SPI master interrupt enable

0: disable

1: enable (Default)

Control HW to make master mode interrupt

1’b1

(POR)

**Note:

1. Bit [1]: When SPI interface is slave mode, SPI interrupt happened when bit [1] ==1, which is written by external

MPU via SPI. Interrupt (HID) would be cleaned once address 0x10 was written.

2. Bit [0]: When SPI interface is master mode, SPI interrupt happened when bit [0] ==1 and every SPI master command

completed. Interrupt (HID) would be cleaned once address 0x10 was written.

6.9.4

SPI Control Register 3

Address: 3fh

Bits

R/W

Bit Mnemonic

Description

default

7-0

R/W

data_len

The data length of read/write,

0000_0000: Reserved

0000_0001: 1 bytes

0000_0010: 2 bytes

0000_0011: 3 bytes

1111_1111:255 bytes

8’d0

(POR)

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