CM6533DH datasheet(44/60 Pages) CMEDIA

44 / 60 page

CM6533,CM6533N,CM6533X1,CM6533DH

USB Audio Chip

Page 44 / 60

www.cmedia.com.tw

Rev.1.6

6.10 GPIO

6.10.1

GPO Data Register

Address Offset: C0-C1h

Bits

R/W

Bit Mnemonic

Description

Default

15:0

R/W

GPO_0_reg

GPO_1_reg

GPO data register which represents

16’h0

(POR)

6.10.2

GPI Data Register

Address Offset: C2-C3h

Bits

R/W

Bit Mnemonic

Description

Default

15:0

GPI data register which represents

16’h0

(POR)

6.10.3

GPIO Direction Control Register

Address Offset: C4-C5h

Bits

R/W

Bit Mnemonic

Description

Default

15:0

R/W

GPOE_0

GPOE_1

GPIO

output

enable

which

represents for pin XGPIO[15:0]

1: the corresponding pins are used as

output

0: the corresponding pins are used as input

16’h0

(POR)

6.10.4

GPIO Interrupt Enable Mask Register

Address Offset: C6-C7h

Bits

R/W

Bit Mnemonic

Description

Default

15:0

R/W

GPI_EN

GPIO_E, GPIO interrupt enable mask which

represents for pins, XGPIO[15:0]

1: enable,

0: disable

16’h0

(POR)

6.10.5

GPIO Debouncing Register

Address Offset: C8-C9h

Default Value: 0000h (MSB -> LSB)

Bits

R/W

Bit Mnemonic

Description

Default

15:0

R/W

GPI_Deb

Enable the clock scale of mini-second (32

ms) for de-bouncing, default 1

1: enable,

0: disable

16’h0

(POR)

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