CM6533DH datasheet(35/60 Pages) CMEDIA

35 / 60 page

CM6533,CM6533N,CM6533X1,CM6533DH

USB Audio Chip

Page 35 / 60

www.cmedia.com.tw

Rev.1.6

6.8.6

I2C Master Data Register

Address: 0x83 ~ 0x92

Bits

R/W

Bit Mnemonic

Description

Default

7-0

R/W

data0~ data15

The data read from or written to the

slave device.

8’b0

(POR)

6.8.7

I2C Master Control and Status Register 0

Address: 0x93

Bits

R/W

Bit Mnemonic

Description

Default

7-0

R/W

i2c_ctrl_reg1

Data length of read/write command

8’h1: 1 byte, minimum length

8’h2: 2 bytes

…

8’hFE: 254 bytes

8’hFF: 256 bytes, maximum length

0x14

(POR)

6.8.8

I2C Master Control and Status Register 1

Address: 0x94

Bits

R/W

Bit Mnemonic

Description

Default

R/W

i2c_start

Trigger I2C read/write command

0->1: trigger I2C read/write command.

1->0: I2C interface had completed

current task.

: I2C interface is idle and ready for

work.

: I2C interface is running.

1’b0

(POR)

R/W

i2c_reset

Reset I2C interface

: Not reset I2C interface

: Reset I2C interface

1’b0

(POR)

R/W

map_len

MAP length

: 8-bit MAP

: 16-bit MAP

1’b0

(POR)

R/W

clk_sync

Clock Synchronization

0: off

1: on, when slave pull-down SCLK,

master would pause

1’b1

(POR)

R/W

fast_std

I2C speed mode

: Standard mode, 100kHz

: Fast mode, 400kHz

1’b0

(POR)

R/W

map_only

MAP only write command

: Write command.

: MAP only write command.

1’b0

(POR)

R/W

auto_rd

Auto read command

: Read command.

: Auto read command.

1’b1

(POR)

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