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CM6533DH Datasheet(PDF) 37 Page - C-Media Electronics |
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CM6533DH Datasheet(HTML) 37 Page - C-Media Electronics |
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37 / 60 page ![]() CM6533,CM6533N,CM6533X1,CM6533DH USB Audio Chip Page 37 / 60 www.cmedia.com.tw Rev.1.6 Copyright© C-Media Electronics Inc. 6.8.10 I2C Master Clock Period Setting Register Address: 0x96 Bits R/W Bit Mnemonic Description Default 7 W CHG_ENABLE MCU can program I2C clock; 1’b1: enable 1’b0 (POR) 6 R/W LD_SEL MCU download select 1’b0 : SPI download 1’b1 : I2C download 1’b0 (POR) 5-0 W CHG_FREQ Set I2C-master clock period. The clock period=83.3*5*(CHG_FREQ+1) Ex: CHG_FREQ = 6’d48 I2C Clock Period=83.3*5*(48+1)=20408ns HW limitation CHG_FREQ >= 6’h3 6’h0 (POR) |
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