LTC4091 datasheet(22/26 Pages) LINER

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LTC4091

4091fa

For more information www.linear.com/LTC4091

APPLICATIONS INFORMATION

the nearest 1% value is 13.3k.

R1 = 0.409 • 13.3k – 0.3467 • 10k = 1.97k

the nearest 1% value is 1.96k. The final solution is shown

in Figure 10 and results in an upper trip point of 55°C and

a lower trip point of –5°C.

Power Dissipation and High Temperature

Considerations

The die temperature of the LTC4091 must be lower than

the maximum rating of 125°C. This is generally not a

concern unless the ambient temperature is above 85°C.

The total power dissipated inside the LTC4091 depends

on many factors, including input voltage, battery voltage,

programmed charge current and load current.

When powered from the primary source, the power dissi-

pation can be estimated by calculating the regulator power

loss from an efficiency measurement, and subtracting the

catch diode loss.

PD =(1− η)• VHVOUT • IBAT+IOUT

(

)

(

)

−VD• 1−

VHVOUT

VVIN

⎛

⎝⎜

⎞

⎠⎟

• IBAT+IOUT

(

)+0.1V •IBAT

where η is the efficiency of the high voltage regulator and

VD is the forward voltage of the catch diode at I = IBAT

+ IOUT. The first term corresponds to the power lost in

converting VVIN to VHVOUT, the second term subtracts the

catch diode loss, and the third term is the power dissipated

inthebatterycharger.Foratypicalapplication,anexample

of this calculation would be:

PD =(1−0.87)• 3.8V •(1A+0.6A)

(

)

−0.4V • 1−

12V

⎛

⎝⎜

⎞

⎠⎟

• 1A +0.6A

(

)+0.1V •1A = 0.46W

This example assumes 87% efficiency, VIN = 12V, VBAT

= 3.7V (VHVOUT is about 3.8V), IBAT = 1A, IOUT = 600mA

resulting in just under 0.5W total dissipation.

It is important to solder the exposed backside of the

package to a ground plane. This ground should be tied to

other copper layers below with thermal vias; these layers

will spread the heat dissipated by the LTC4091. Additional

vias should be placed near the catch diode. Adding more

coppertothetopandbottomlayersandtyingthiscopperto

the internal planes with vias can reduce thermal resistance

further. With these steps, the thermal resistance from die

(i.e., junction) to ambient can be reduced to θJA = 40°C/W.

Board Layout Considerations

As discussed in the previous section, it is critical that the

exposedmetalpadonthebacksideoftheLTC4091package

be soldered to the PC board ground. Furthermore, proper

operation and minimum EMI requires a careful printed

circuit board (PCB) layout. Note that large, switched cur-

rents flow in the power switch (between the VIN and SW

pins), the catch diode and the VIN input capacitor. These

components,alongwiththeinductorandoutputcapacitor,

should be placed on the same side of the circuit board,

and their connections should be made on that layer. Place

a local, unbroken ground plane below these components.

The loop formed by these components should be as small

as possible.

Additionally, the SW and BOOST nodes should be kept

as small as possible. Linear Technology demonstration

board DC2558A shows an example of a preferred printed

circuit board layout. Gerber files can be downloaded at:

http://www.linear.com/product/LTC4091#demoboards.

High frequency currents, such as the high voltage in-

put current of the LTC4091, tend to find their way along

the ground plane on a mirror path directly beneath the

incident path on the top of the board. If there are slits or

cuts in the ground plane due to other traces on that layer,

the current will be forced to go around the slits. If high

frequency currents are not allowed to flow back through

their natural least-area path, excessive voltage will build

up and radiated emissions will occur. See Figure 10.

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