LTC2602 datasheet(6/32 Pages) LINER

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LTC2320-12

Rev B

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground, or above VDD or

OVDD, they will be clamped by internal diodes. This product can handle input

currents up to 100mA below ground, or above VDD or OVDD, without latch-up.

Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 1.5MHz.

Note 5: Recommended operating conditions.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code flickers between 0000 0000 0000 0 and 1111 1111

1111 1. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed

deviation from ideal first and last code transitions and includes the effect

of offset error.

Note 8: All specifications in dB are referred to a full-scale ±4.096V input

with REF = 4.096V.

Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer

must be turned off by setting REFBUFEN = 0V.

Note 10: fSMPL = 1.5MHz, IREFOUT1,2,3,4 varies proportionally with sample rate.

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V.

Note 13: tSCK of 9.1ns allows a shift clock frequency up to 105MHz for

rising edge capture.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 15: CNV is driven from a low jitter digital source, typically at OVDD

logic levels.

ADC TIMING CHARACTERISTICS The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

tDCNVSDOZ

Bus Relinquish Time After CNV↑

(Note 11)

tDCNVSDOV

SDO Valid Delay from CNV↓

(Note 11)

tDSCKHCNVH

SCK Delay Time to CNV↑

(Note 11)

CMOS I/O Mode, DDR

CMOS/LVDS = GND, SDR/ DDR = OVDD

tSCK

SCK Period

18.2

tSCKH

SCK High Time

8.2

tSCKL

SCK Low Time

8.2

tHSDO_DDR

SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12)

1.5

tDSCKCLKOUT SCK to CLKOUT Delay

(Note 12)

4.5

tDCNVSDOZ

Bus Relinquish Time After CNV↑

(Note 11)

tDCNVSDOV

SDO Valid Delay from CNV↓

(Note 11)

tDSCKHCNVH

SCK Delay Time to CNV↑

(Note 11)

LVDS I/O Mode, SDR

CMOS/LVDS = OVDD, SDR/DDR = GND

tSCK

SCK Period

3.3

tSCKH

SCK High Time

1.5

tSCKL

SCK Low Time

1.5

tHSDO_SDR

SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF OVDD = 2.5V

1.5

tDSCKCLKOUT SCK to CLKOUT Delay

OVDD = 2.5V

tDSCKHCNVH

SCK Delay Time to CNV↑

(Note 11)

LVDS I/O Mode, DDR

CMOS/LVDS = OVDD, SDR/DDR = OVDD

tSCK

SCK Period

6.6

tSCKH

SCK High Time

tSCKL

SCK Low Time

tHSDO_DDR

SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF OVDD = 2.5V

1.5

tDSCKCLKOUT SCK to CLKOUT Delay

OVDD = 2.5V

tDSCKHCNVH

SCK Delay Time to CNV↑

(Note 11)

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