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LTC2320-12

Rev B

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APPLICATIONS INFORMATION

the SCK pin to achieve 1.5Msps throughput using all eight

SDO outputs. In DDR mode (SDR/DDR Pin 23 = OVDD),

each input edge of SCK shifts the conversion result MSB

first onto the SDO pins. A 50MHz external clock must be

applied at the SCK pin to achieve 1.5Msps throughput

using all eight SDO1 through SDO8 outputs.

CLKOUT Serial Data Clock Output

The CLKOUT output provides a skew-matched clock to

latch the SDO output at the receiver. The timing skew

of the CLKOUT and SDO outputs are matched. For high

throughput applications, using CLKOUT instead of SCK to

capture the SDO output eases timing requirements at the

receiver. For low throughput speed applications, CLKOUT

can be disabled by tying Pin 34 to OVDD.

Nap/Sleep Modes

Nap mode is a method to save power without sacrificing

power-up delays for subsequent conversions. Sleep mode

has substantial power savings, but a power-up delay is

incurred to allow the reference and power systems to

become valid. To enter nap mode on the LTC2320-12,

the SCK signal must be held high or low and a series of

two CNV pulses must be applied. This is the case for both

CMOS and LVDS modes. The second rising edge of CNV

initiates the nap state. The nap state will persist until either

asinglerisingedgeofSCKisapplied,orfurtherCNVpulses

are applied. The SCK rising edge will put the LTC2320-12

back into the operational (full-power) state. When in nap

mode, two additional pulses will put the LTC2320-12 in

sleep mode. When configured for CMOS I/O operation, a

single rising edge of SCK can return the LTC2320-12 into

operational mode. A 10ms delay is necessary after exiting

sleep mode to allow the reference buffer to recharge the

external filter capacitor. In LVDS mode, exit sleep mode

by supplying a fifth CNV pulse. The fifth pulse will return

the LTC2320-12 to operational mode, and further SCK

pulses will keep the part from re-entering nap and sleep

modes. The fifth SCK pulse also works in CMOS mode

as a method to exit sleep. In the absence of SCK pulses,

repetitive CNV pulses will cycle the LTC2320-12 between

operational, nap and sleep modes indefinitely.

Refer to the timing diagrams in Figure 18, Figure 19,

Figure 20 and Figure 21 for more detailed timing informa-

tion about sleep and nap modes.

Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK

FULL POWER MODE

CNV

SCK

HOLD STATIC HIGH OR LOW

NAP MODE

SDO1 – 8

WAKE ON 1ST SCK EDGE

232012 F18

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