LTC2602 datasheet(27/32 Pages) LINER

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LTC2320-12

Rev B

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APPLICATIONS INFORMATION

Figure 22. LTC2320-12 Using the LVDS Interface

Figure 23. LTC2320-12 Using the LVDS Interface with One Lane

100

2.5V

OVDD

LTC2320-12

FPGA OR DSP

232012 F22

SCK+

SCK–

SDOD+

SDOD–

SDOC+

SDOC–

SDOB+

SDOB–

SDOA+

SDOA–

CMOS/LVDS

–

100

–

100

–

100

–

100

–

100

CLKOUT+

CLKOUT–

CNV

RETIMING

FLIP-FLOP

100

2.5V

OVDD

LTC2320-12

FPGA OR DSP

232012 F23

SCK+

SCK–

SDOD+

SDOD–

SDOC+

SDOC–

SDOB+

SDOB–

SDOA+

SDOA–

CMOS/LVDS

–

100

–

100

CLKOUT+

CLKOUT–

CNV

RETIMING

FLIP-FLOP

DIGITAL INTERFACE

The LTC2320-12 features a serial digital interface that

is simple and straightforward to use. The flexible OVDD

supply allows the LTC2320-12 to communicate with any

digital logic operating between 1.8V and 2.5V. In addi-

tion to a standard CMOS SPI interface, the LTC2320-12

provides an optional LVDS SPI interface to support low

noise digital design. The CMOS /LVDS pin is used to select

the digital interface mode. The SCK input clock shifts the

conversion result MSB first on the SDO pins. CLKOUT

provides a skew-matched clock to latch the SDO output

at the receiver. The timing skew of the CLKOUT and SDO

outputs are matched. For high throughput applications,

using CLKOUT instead of SCK to capture the SDO output

eases timing requirements at the receiver. In CMOS mode,

use the SDO1 – SDO8, and CLKOUT pins as outputs. Use

the SCK pin as an input. In LVDS mode, use the SDOA+/

SDOA– through SDOD+/SDOD– and CLKOUT+/CLKOUT–

pins as differential outputs. Each LVDS lane yields two

channels worth of data: SDOA yields CH1 and CH2 data,

SDOB yields CH3 and CH4 data, SDOC yields CH5 and CH6

data and SDOD yields CH7 and CH8 data. These pins must

be differentially terminated by an external 100Ω resistor at

the receiver (FPGA). The SCK+/SCK– pins are differential

inputs and must be terminated differentially by an external

100Ω resistor at the receiver(ADC).

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