LTC2602 datasheet(10/32 Pages) LINER

10 / 32 page

LTC2320-12

Rev B

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PIN FUNCTIONS

Pins that are the same for all digital I/O modes.

AIN6+, AIN6– (Pins 2, 1): Analog Differential Input Pins.

Full-scale range (AIN6+ – AIN6–) is ±REFOUT3 voltage.

These pins can be driven from VDD to GND.

GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.

These pins and exposed pad (Pin 53) must be tied directly

to a solid ground plane.

AIN5+, AIN5– (Pins 5, 4): Analog Differential Input Pins.

Full-scale range (AIN5+ – AIN5–) is ±REFOUT3 voltage.

These pins can be driven from VDD to GND.

REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

REF (Pin 8): Common 4.096V reference output. Decouple

to GND with a 1μF low ESR ceramic capacitor. May be

overdriven with a single external reference to establish a

common reference for ADC cores 1 through 4.

REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

AIN4+, AIN4– (Pins 11, 10): Analog Differential Input Pins.

Full-scale range (AIN4+ – AIN4–) is ±REFOUT2 voltage.

These pins can be driven from VDD to GND.

AIN3+, AIN3– (Pins 14, 13): Analog Differential Input Pins.

Full-scale range (AIN3+ – AIN3–) is ±REFOUT2 voltage.

These pins can be driven from VDD to GND.

VDD (Pins 15, 21, 44, 52): Power Supply. Bypass VDD to

GND with a 10µF ceramic capacitor and a 0.1µF ceramic

capacitor close to the part. The VDDpinsshouldbeshorted

together and driven from the same supply.

AIN2+, AIN2– (Pins 17, 16): Analog Differential Input Pins.

Full-scale range (AIN2+ – AIN2–) is ±REFOUT1 voltage.

These pins can be driven from VDD to GND.

AIN1+, AIN1– (Pins 20, 19): Analog Differential Input Pins.

Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage.

These pins can be driven from VDD to GND.

REFOUT1(Pin22):ReferenceBuffer1Output.Anonboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

SDR/DDR (Pin 23): Double Data Rate Input. Controls the

frequency of SCK and CLKOUT. Tie to GND for the falling

edge of SCK to shift each serial data output (Single Data

Rate, SDR). Tie to OVDD to shift serial data output on each

edge of SCK (Double Data Rate, DDR). CLKOUT will be a

delayed version of SCK for both pin states.

CNV (Pin 24): Convert Input. This pin, when high, defines

the acquisition phase. When this pin is driven low, the

conversion phase is initiated and output data is clocked

out. This input must be driven at OVDD levels with a low

jitter pulse. This pin is unaffected by the CMOS/LVDS pin.

CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin

to enable CMOS mode, tie to OVDD to enable LVDS mode.

Float this pin to enable low power LVDS mode.

OVDD (Pins 31, 37): I/O Interface Digital Power. The range

of OVDD is 1.71V to 2.63V. This supply is nominally set

to the same supply as the host interface (CMOS: 1.8V or

2.5V, LVDS: 2.5V). Bypass OVDD to GND (Pins 32 and 38)

with 0.1µF capacitors.

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