LTC2602 datasheet(12/32 Pages) LINER

12 / 32 page

LTC2320-12

Rev B

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SDO7 (Pin 39): CMOS Serial Data Output for ADC Chan-

nel 7. The conversion result is shifted MSB first on each

falling edge of SCK in SDR mode and each SCK edge in

DDR mode. 13 SCK edges are required for 13-bit conver-

sion data to be read from SDO7 in SDR mode, 13 SCK

edges in DDR mode. Supplying more clocks will yield

data from subsequent channels (CH8, CH1, CH2, CH3,

CH4, CH5, CH6).

SDO8 (Pin 40): CMOS Serial Data Output for ADC Chan-

nel 8. The conversion result is shifted MSB first on each

falling edge of SCK in SDR mode and each SCK edge in

DDR mode. 13 SCK edges are required for 13-bit conver-

sion data to be read from SDO8 in SDR mode, 13 SCK

edges in DDR mode. Supplying more clocks will yield

data from subsequent channels (CH1, CH2, CH3, CH4,

CH5, CH6, CH7).

SCK (Pin 41): Serial Data Clock Input. The falling edge

of this clock shifts the conversion result MSB first onto

the SDO pins in SDR mode (DDR = LOW). In DDR mode

(SDR/DDR = HIGH) each edge of this clock shifts the

conversion result MSB first onto the SDO pins. The logic

level is determined by OVDD.

DNC (Pin 42): In CMOS mode do not connect this pin.

LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR

FLOAT)

SDOA+, SDOA– (Pins 27, 28): LVDS Serial Data Output for

ADCChannels1and2.TheconversionresultisshiftedCH1

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 32 SCK edges are required

for 13-bit conversion data to be read from AIN1 and AIN2

on SDOA in SDR mode, 13 SCK edges in DDR mode.

Supplying more clocks will yield data from subsequent

channels (CH3, CH4, CH5, CH6, CH7, CH8).Terminate

with a 100Ω resistor at the receiver (FPGA).

SDOB+, SDOB– (Pins 29, 30): LVDS Serial Data Output for

ADCChannels3and4.TheconversionresultisshiftedCH3

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 32 SCK edges are required

for 13-bit conversion data to be read from AIN3 and AIN4

on SDOB in SDR mode, 13 SCK edges in DDR mode.

Supplying more clocks will yield data from subsequent

channels (CH5, CH6, CH7, CH8, CH1, CH2).Terminate

with a 100Ω resistor at the receiver (FPGA).

CLKOUT+, CLKOUT– (Pins 33, 34): Serial Data Clock

Output. CLKOUT provides a skew-matched clock to

latch the SDO output at the receiver. These pins echo the

input at SCK with a small delay. These pins must be dif-

ferentially terminated by an external 100Ω resistor at the

receiver (FPGA).

SDOC+, SDOC– (Pins 35, 36): LVDS Serial Data Output for

ADCchannels5and6.TheconversionresultisshiftedCH5

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 32 SCK edges are required

for 13-bit conversion data to be read from AIN5 and AIN6

on SDOA in SDR mode, 13 SCK edges in DDR mode.

Supplying more clocks will yield data from subsequent

channels (CH7, CH8, CH1, CH2, CH3, CH4).Terminate

with a 100Ω resistor at the receiver (FPGA).

SDOD+, SDOD– (Pins 39, 40): LVDS Serial Data Output

for ADC Channels 7 and 8. The conversion result is shifted

CH7 MSB first on each falling edge of SCK in SDR mode

and each SCK edge in DDR mode. 32 SCK edges are re-

quired for 13-bit conversion data to be read from AIN7 and

AIN8 on SDOA in SDR mode, 13 SCK edges in DDR mode.

Supplying more clocks will yield data from subsequent

channels (CH1, CH2, CH3, CH4, CH5, CH6).Terminate

with a 100Ω resistor at the receiver (FPGA).

SCK+, SCK– (Pins 41, 42): Serial Data Clock Input. The

falling edge of this clock shifts the conversion result MSB

first onto the SDO pins in SDR mode (SDR/DDR = LOW).

In DDR mode (SDR/DDR = HIGH) each edge of this clock

shifts the conversion result MSB first onto the SDO pins.

These pins must be differentially terminated by an external

100Ω resistor at the receiver (ADC).

PIN FUNCTIONS

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